From patchwork Mon Oct 30 20:17:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 10033065 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 867026039A for ; Mon, 30 Oct 2017 20:17:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A24B23B34 for ; Mon, 30 Oct 2017 20:17:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6F17928854; Mon, 30 Oct 2017 20:17:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1865023B34 for ; Mon, 30 Oct 2017 20:17:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ADEEA89DA4; Mon, 30 Oct 2017 20:17:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 31E556E4BE for ; Mon, 30 Oct 2017 20:17:18 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP; 30 Oct 2017 13:17:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,321,1505804400"; d="scan'208";a="169689623" Received: from omateolo-linux.fm.intel.com ([10.1.27.13]) by fmsmga006.fm.intel.com with ESMTP; 30 Oct 2017 13:17:16 -0700 From: Oscar Mateo To: intel-gfx@lists.freedesktop.org Date: Mon, 30 Oct 2017 13:17:17 -0700 Message-Id: <1509394647-23209-11-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509394647-23209-1-git-send-email-oscar.mateo@intel.com> References: <1509394647-23209-1-git-send-email-oscar.mateo@intel.com> MIME-Version: 1.0 Cc: Rodrigo Vivi Subject: [Intel-gfx] [PATCH 10/20] drm/i915/cnl: Move GT and Display workarounds from init_clock_gating X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP To their rightful place inside intel_workarounds.c v2: classify WaSarbUnitClockGatingDisable as GT WA (Ville) Signed-off-by: Oscar Mateo Reviewed-by: Chris Wilson (v1) Cc: Rodrigo Vivi Cc: Mika Kuoppala Cc: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 32 +------------------------------- drivers/gpu/drm/i915/intel_workarounds.c | 26 +++++++++++++++++++++++++- 2 files changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0d0e84b..ff3ac6c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8519,36 +8519,6 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) CNP_PWM_CGE_GATING_DISABLE); } -static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) -{ - u32 val; - cnp_init_clock_gating(dev_priv); - - /* This is not an Wa. Enable for better image quality */ - I915_WRITE(_3D_CHICKEN3, - _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE)); - - /* WaEnableChickenDCPR:cnl */ - I915_WRITE(GEN8_CHICKEN_DCPR_1, - I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); - - /* WaFbcWakeMemOn:cnl */ - I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | - DISP_FBC_MEMORY_WAKE); - - /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */ - if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) - I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, - I915_READ(SLICE_UNIT_LEVEL_CLKGATE) | - SARBUNIT_CLKGATE_DIS); - - /* Display WA #1133: WaFbcSkipSegments:cnl */ - val = I915_READ(ILK_DPFC_CHICKEN); - val &= ~GLK_SKIP_SEG_COUNT_MASK; - val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1); - I915_WRITE(ILK_DPFC_CHICKEN, val); -} - static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) { cnp_init_clock_gating(dev_priv); @@ -9040,7 +9010,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) { if (IS_CANNONLAKE(dev_priv)) - dev_priv->display.init_clock_gating = cnl_init_clock_gating; + dev_priv->display.init_clock_gating = nop_init_clock_gating; else if (IS_COFFEELAKE(dev_priv)) dev_priv->display.init_clock_gating = cfl_init_clock_gating; else if (IS_SKYLAKE(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 3e643b6..82defb1 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -724,6 +724,15 @@ static int cfl_gt_workarounds_init_early(struct drm_i915_private *dev_priv) static int cnl_gt_workarounds_init_early(struct drm_i915_private *dev_priv) { + /* This is not an Wa. Enable for better image quality */ + GT_WA_SET_BIT_MASKED(_3D_CHICKEN3, + _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); + + /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */ + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) + GT_WA_SET_BIT(SLICE_UNIT_LEVEL_CLKGATE, + SARBUNIT_CLKGATE_DIS); + /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */ if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0)) GT_WA_SET_BIT(GAMT_CHKN_BIT_REG, @@ -856,6 +865,22 @@ static int cfl_display_workarounds_init_early(struct drm_i915_private *dev_priv) static int cnl_display_workarounds_init_early(struct drm_i915_private *dev_priv) { + if (HAS_PCH_CNP(dev_priv)) { + /* Wa #1181 */ + DISPLAY_WA_SET_BIT(SOUTH_DSPCLK_GATE_D, + CNP_PWM_CGE_GATING_DISABLE); + } + + /* WaEnableChickenDCPR:cnl */ + DISPLAY_WA_SET_BIT(GEN8_CHICKEN_DCPR_1, MASK_WAKEMEM); + + /* WaFbcWakeMemOn:cnl */ + DISPLAY_WA_SET_BIT(DISP_ARB_CTL, DISP_FBC_MEMORY_WAKE); + + /* Display WA #1133: WaFbcSkipSegments:cnl */ + DISPLAY_WA_SET_FIELD(ILK_DPFC_CHICKEN, GLK_SKIP_SEG_COUNT_MASK, + GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1)); + return 0; } @@ -863,7 +888,6 @@ static int display_workarounds_init_early(struct drm_i915_private *dev_priv) { int err; - DISPLAY_WA_SET_BIT(_MMIO(0), 0); /* shut up gcc temporarily */ dev_priv->workarounds.display_wa_count = 0; if (INTEL_GEN(dev_priv) < 8)