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[RFC,17/20] drm/i915/skl: Move GT and Display workarounds from init_clock_gating

Message ID 1509732588-10599-18-git-send-email-oscar.mateo@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

oscar.mateo@intel.com Nov. 3, 2017, 6:09 p.m. UTC 
To their rightful place inside intel_workarounds.c

v2: Static tables (Joonas)

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v1)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c          | 15 +--------------
 drivers/gpu/drm/i915/intel_workarounds.c |  8 ++++++++
 2 files changed, 9 insertions(+), 14 deletions(-)
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Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 98e976e..eb5bac0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8417,17 +8417,6 @@  static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
-static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-	/* WAC6entrylatency:skl */
-	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
-		   FBC_LLC_FULLY_OPEN);
-
-	/* WaFbcNukeOnHostModify:skl */
-	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
-		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
-}
-
 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	/* The GTT cache must be disabled if the system is using 2M pages. */
@@ -8878,10 +8867,8 @@  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
 	    IS_GEMINILAKE(dev_priv) || IS_KABYLAKE(dev_priv)   ||
-	    IS_BROXTON(dev_priv))
+	    IS_BROXTON(dev_priv)    || IS_SKYLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = nop_init_clock_gating;
-	else if (IS_SKYLAKE(dev_priv))
-		dev_priv->display.init_clock_gating = skl_init_clock_gating;
 	else if (IS_BROADWELL(dev_priv))
 		dev_priv->display.init_clock_gating = bdw_init_clock_gating;
 	else if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 1ebe56d..0e3f7c3 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -932,6 +932,14 @@  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	{ WA_DISP("WaDisableDopClockGating"),
 	  ALL_REVS, REG(GEN7_MISCCPCTL),
 	  CLEAR_BIT(GEN7_DOP_CLOCK_GATE_ENABLE) },
+
+	{ WA_DISP("WAC6entrylatency"),
+	  ALL_REVS, REG(FBC_LLC_READ_CTRL),
+	  SET_BIT(FBC_LLC_FULLY_OPEN) },
+
+	{ WA_DISP("WaFbcNukeOnHostModify"),
+	  ALL_REVS, REG(ILK_DPFC_CHICKEN),
+	  SET_BIT(ILK_DPFC_NUKE_ON_ANY_MODIFICATION) },
 };
 
 static struct i915_wa_reg bxt_disp_was[] = {