From patchwork Fri Nov 3 18:09:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: oscar.mateo@intel.com X-Patchwork-Id: 10041001 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 30811602D8 for ; Fri, 3 Nov 2017 18:09:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2898B28F73 for ; Fri, 3 Nov 2017 18:09:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1D85028F9E; Fri, 3 Nov 2017 18:09:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7D0D528F73 for ; Fri, 3 Nov 2017 18:09:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A7EAA6EB03; Fri, 3 Nov 2017 18:09:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id C95906EAED for ; Fri, 3 Nov 2017 18:09:41 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP; 03 Nov 2017 11:09:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,339,1505804400"; d="scan'208";a="169033935" Received: from omateolo-linux.fm.intel.com ([10.1.27.13]) by orsmga005.jf.intel.com with ESMTP; 03 Nov 2017 11:09:35 -0700 From: Oscar Mateo To: intel-gfx@lists.freedesktop.org Date: Fri, 3 Nov 2017 11:09:36 -0700 Message-Id: <1509732588-10599-9-git-send-email-oscar.mateo@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509732588-10599-1-git-send-email-oscar.mateo@intel.com> References: <1509732588-10599-1-git-send-email-oscar.mateo@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC PATCH 08/20] drm/i915: Print all workaround types correctly in debugfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Let's try to make sure that all WAs are applied correctly and survive resumes, resets, etc... (with some help from a companion i-g-t patch). v2: - Rebased - Print display WAs as well (Ville) v3: - Grab the forcewake once for everyone, so that all reads are from the same powercontext (Chris) v4: Rebase on top of static tables Signed-off-by: Oscar Mateo Cc: Chris Wilson Cc: Mika Kuoppala Cc: Ville Syrjälä --- drivers/gpu/drm/i915/i915_debugfs.c | 79 +++++++++++++++++++++++++++++-------- 1 file changed, 63 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 12c4330..8a6fef4 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3356,48 +3356,95 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) return 0; } +static void check_wa_register(struct seq_file *m, + const struct i915_wa_reg *wa_reg) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + u32 read; + bool ok; + + assert_forcewakes_active(dev_priv, FORCEWAKE_ALL); + + read = I915_READ_FW(wa_reg->addr); + ok = (wa_reg->value & wa_reg->mask) == (read & wa_reg->mask); + seq_printf(m, + "0x%X: 0x%08x, mask: 0x%08x, read: 0x%08x, status: %s, name: %s\n", + i915_mmio_reg_offset(wa_reg->addr), + wa_reg->value, wa_reg->mask, read, + ok ? "OK" : "FAIL", wa_reg->name); +} + +static void check_wa_registers(struct seq_file *m, + const struct i915_wa_reg_table *wa_table, + uint table_count) +{ + int i, j; + + for (i = 0; i < table_count; i++) { + const struct i915_wa_reg *wa = wa_table[i].table; + + for (j = 0; j < wa_table[i].count; j++) { + if (!wa[j].applied) + continue; + + check_wa_register(m, &wa[j]); + } + } +} + static int i915_wa_registers(struct seq_file *m, void *unused) { - struct intel_engine_cs *engine; struct drm_i915_private *dev_priv = node_to_i915(m->private); struct drm_device *dev = &dev_priv->drm; struct i915_workarounds *workarounds = &dev_priv->workarounds; const struct i915_wa_reg_table *wa_table; uint table_count; - enum intel_engine_id id; int i, j, ret; - intel_ctx_workarounds_get(dev_priv, &wa_table, &table_count); - ret = mutex_lock_interruptible(&dev->struct_mutex); if (ret) return ret; intel_runtime_pm_get(dev_priv); - seq_printf(m, "Workarounds applied: %d\n", workarounds->ctx_count); - for_each_engine(engine, dev_priv, id) - seq_printf(m, "HW whitelist count for %s: %d\n", - engine->name, workarounds->hw_whitelist_count[id]); - + seq_printf(m, "Context workarounds applied: %d\n", + workarounds->ctx_count); + intel_ctx_workarounds_get(dev_priv, &wa_table, &table_count); for (i = 0; i < table_count; i++) { const struct i915_wa_reg *wa = wa_table[i].table; for (j = 0; j < wa_table[i].count; j++) { - u32 read; - bool ok; - if (!wa[j].applied) continue; - read = I915_READ(wa[j].addr); - ok = (wa[j].value & wa[j].mask) == (read & wa[j].mask); seq_printf(m, - "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s, name: %s\n", + "0x%X: 0x%08X, mask: 0x%08X, name: %s\n", i915_mmio_reg_offset(wa[j].addr), wa[j].value, - wa[j].mask, read, ok ? "OK" : "FAIL", wa[j].name); + wa[j].mask, wa[j].name); } } + seq_putc(m, '\n'); + + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + + seq_printf(m, "GT workarounds applied: %d\n", workarounds->gt_count); + intel_gt_workarounds_get(dev_priv, &wa_table, &table_count); + check_wa_registers(m, wa_table, table_count); + seq_putc(m, '\n'); + + seq_printf(m, "Display workarounds applied: %d\n", + workarounds->disp_count); + intel_display_workarounds_get(dev_priv, &wa_table, &table_count); + check_wa_registers(m, wa_table, table_count); + seq_putc(m, '\n'); + + seq_printf(m, "Whitelist workarounds applied: %d\n", + workarounds->hw_whitelist_count[RCS]); + intel_whitelist_workarounds_get(dev_priv, &wa_table, &table_count); + check_wa_registers(m, wa_table, table_count); + seq_putc(m, '\n'); + + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); intel_runtime_pm_put(dev_priv); mutex_unlock(&dev->struct_mutex);