From patchwork Tue Nov 14 18:53:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sundaresan, Sujaritha" X-Patchwork-Id: 10058131 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9503D602A7 for ; Tue, 14 Nov 2017 18:57:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8964A29981 for ; Tue, 14 Nov 2017 18:57:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7E40D29985; Tue, 14 Nov 2017 18:57:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 164FE29981 for ; Tue, 14 Nov 2017 18:57:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 92FEE6E210; Tue, 14 Nov 2017 18:57:57 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4685F6E210 for ; Tue, 14 Nov 2017 18:57:56 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Nov 2017 10:57:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.44,395,1505804400"; d="scan'208"; a="1244038683" Received: from sujaritha-z170x-ud5.fm.intel.com ([10.1.27.118]) by fmsmga002.fm.intel.com with ESMTP; 14 Nov 2017 10:57:52 -0800 From: Sujaritha Sundaresan To: intel-gfx@lists.freedesktop.org Date: Tue, 14 Nov 2017 10:53:38 -0800 Message-Id: <1510685618-5866-1-git-send-email-sujaritha.sundaresan@intel.com> X-Mailer: git-send-email 1.9.1 Cc: Sujaritha Sundaresan Subject: [Intel-gfx] [PATCH v10 1/1] drm/i915 : Unifying seq_puts messages for feature support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Unifying the various seq_puts messages in debugfs to a common one for feature support. v2: Clarifying the commit message (Anusha) v3: Re-factoring code as per review (Michal) v4: Rebase v5: Split from following patch v6: Re-factoring code (Michal, Sagar) Clarifying commit message (Sagar) v7: Generalizing subject to drm/i915 (Sagar) v8: Omitting DRRS seq_puts unification (Michal) v9: Including the HAS_HUC condition (Michal) Updating more functions with unified message (Sagar) v10: Sepearating from patch series Reverting macro changes Suggested by : Michal Wajdeczko Signed-off-by: Sujaritha Sundaresan Cc: Anusha Srivatsa Cc: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Oscar Mateo Cc: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_debugfs.c | 49 +++++++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index ff8f508..a029842 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1641,7 +1641,7 @@ static int i915_fbc_status(struct seq_file *m, void *unused) struct drm_i915_private *dev_priv = node_to_i915(m->private); if (!HAS_FBC(dev_priv)) { - seq_puts(m, "FBC unsupported on this chipset\n"); + seq_puts(m, "not supported\n"); return 0; } @@ -1809,7 +1809,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) unsigned int max_gpu_freq, min_gpu_freq; if (!HAS_LLC(dev_priv)) { - seq_puts(m, "unsupported on this chipset\n"); + seq_puts(m, "not supported\n"); return 0; } @@ -2360,8 +2360,10 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = node_to_i915(m->private); struct drm_printer p; - if (!HAS_HUC_UCODE(dev_priv)) + if (!HAS_HUC_UCODE(dev_priv)) { + seq_puts(m, "not supported\n"); return 0; + } p = drm_seq_file_printer(m); intel_uc_fw_dump(&dev_priv->huc.fw, &p); @@ -2379,8 +2381,10 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data) struct drm_printer p; u32 tmp, i; - if (!HAS_GUC_UCODE(dev_priv)) + if (!HAS_GUC_UCODE(dev_priv)) { + seq_puts(m, "not supported\n"); return 0; + } p = drm_seq_file_printer(m); intel_uc_fw_dump(&dev_priv->guc.fw, &p); @@ -2460,9 +2464,11 @@ static bool check_guc_submission(struct seq_file *m) if (!guc->execbuf_client) { seq_printf(m, "GuC submission %s\n", + HAS_GUC(dev_priv) ? + "not supported" : HAS_GUC_SCHED(dev_priv) ? "disabled" : - "not supported"); + "failed"); return false; } @@ -2651,7 +2657,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) bool enabled = false; if (!HAS_PSR(dev_priv)) { - seq_puts(m, "PSR not supported\n"); + seq_puts(m, "not supported\n"); return 0; } @@ -2828,7 +2834,7 @@ static int i915_runtime_pm_status(struct seq_file *m, void *unused) struct pci_dev *pdev = dev_priv->drm.pdev; if (!HAS_RUNTIME_PM(dev_priv)) - seq_puts(m, "Runtime power management not supported\n"); + seq_puts(m, "not supported\n"); seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); seq_printf(m, "IRQs disabled: %s\n", @@ -3432,9 +3438,12 @@ static int i915_ipc_status_show(struct seq_file *m, void *data) static int i915_ipc_status_open(struct inode *inode, struct file *file) { struct drm_i915_private *dev_priv = inode->i_private; + struct seq_file *m; - if (!HAS_IPC(dev_priv)) - return -ENODEV; + if (!HAS_IPC(dev_priv)) { + seq_puts(m, "not supported\n"); + return 0; + } return single_open(file, i915_ipc_status_show, dev_priv); } @@ -3939,9 +3948,12 @@ static int cur_wm_latency_show(struct seq_file *m, void *data) static int pri_wm_latency_open(struct inode *inode, struct file *file) { struct drm_i915_private *dev_priv = inode->i_private; + struct seq_file *m; - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) - return -ENODEV; + if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { + seq_puts(m, "not supported\n"); + return 0; + } return single_open(file, pri_wm_latency_show, dev_priv); } @@ -3949,9 +3961,13 @@ static int pri_wm_latency_open(struct inode *inode, struct file *file) static int spr_wm_latency_open(struct inode *inode, struct file *file) { struct drm_i915_private *dev_priv = inode->i_private; + struct seq_file *m; + + if (HAS_GMCH_DISPLAY(dev_priv)) { + seq_puts(m, "not supported\n"); + return 0; + } - if (HAS_GMCH_DISPLAY(dev_priv)) - return -ENODEV; return single_open(file, spr_wm_latency_show, dev_priv); } @@ -3959,9 +3975,12 @@ static int spr_wm_latency_open(struct inode *inode, struct file *file) static int cur_wm_latency_open(struct inode *inode, struct file *file) { struct drm_i915_private *dev_priv = inode->i_private; + struct seq_file *m; - if (HAS_GMCH_DISPLAY(dev_priv)) - return -ENODEV; + if (HAS_GMCH_DISPLAY(dev_priv)) { + seq_puts(m, "not supported\n"); + return 0; + } return single_open(file, cur_wm_latency_show, dev_priv); }