| Message ID | 1511972351-574-4-git-send-email-sagar.a.kamble@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
>-----Original Message----- >From: Kamble, Sagar A >Sent: Wednesday, November 29, 2017 8:19 AM >To: intel-gfx@lists.freedesktop.org >Cc: Kamble, Sagar A <sagar.a.kamble@intel.com>; Mcgee, Jeff ><jeff.mcgee@intel.com>; Spotswood, John A <john.a.spotswood@intel.com>; >Srivatsa, Anusha <anusha.srivatsa@intel.com>; Wajdeczko, Michal ><Michal.Wajdeczko@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; Joonas >Lahtinen <joonas.lahtinen@linux.intel.com> >Subject: [PATCH v2 3/3] drm/i915/guc: Change default GuC FW for KBL to v9.39 > >This patch makes v9.39 firmware as default firmware for KBL. > >Note: GuC logging control is changed with this firmware. GuC is expecting i915 to >set control bit to enable "default logging" >while using GuC action UK_LOG_ENABLE_LOGGING. >However i915 is currently not doing this because it is version specific change and >can be handled entirely in GuC. It will need to be fixed in future firmwares. > >This update includes (since v9.14): > >- DCC spec changes for BXT + DCT enabling >- Bug Fix for power conservation feature SLPC_DCC >- Scheduler 1-element submission during DCC cycles. >- SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC >- Moving GuC non_critical r/w data to lower SRAM 64KB >- Media engine Reset fix. Correctly marking context for resubmission in > Media Reset case. >- ABT Disable bug fix. Disabled Evaluation mode on context change. >- Async FW in Engine Schedule feature (not enabled from KMD) >- GuC clean up to align developer build in line to production build. >- Disable ARAT interrupt before programming ARAT delta. >- Memory range check in Parse to avoid failure due to overflow. >- GuC Msg Channel Hang WA - Stall GUC for mmio access when IDI is low > during CPD flow. >- Fix for submit queue over flow issue >- Enabling IBC on KBL GT3 15W, GT4 45W >- Disabling wrong device ID WA in production signed kernel >- Enabling WA for MSGCH hang issue upto required KBL stepping >- Clear forcewake in CSB when SQ is empty. >- 3Tries of GuC2CSME wake request >- During reset one parameter was not getting accounted >- Disable DCC 1-elem mode submission >- Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder. >- This is file location change.No functional change done as part of this > check in. >- Enabling Guc Log changes for ultra low logging for OCA >- Enabling Dynamic Render Power Well Hysteresis Programming for Compute > Worklaods >- Enabling build failure check to catch critical section overflow. >- Disable build.bat redundant prints. >- Move few least used functions to non-critical section. >- Rearrange GuC documentation folder structure. >- Synchronize SLPC internal debug interface with other branches. >- Fixing Issue with Default Guc Log changes for OCA using special Control > Bit >- Aggressive DCC implementation for supported platforms. > >v2: Rebase. Updated commit message. > >Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> >Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> >Cc: Spotswood John A <john.a.spotswood@intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> >Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> >Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Anusha Srivatsa<anusha.srivatsa@intel.com > > drivers/gpu/drm/i915/intel_guc_fw.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c >b/drivers/gpu/drm/i915/intel_guc_fw.c >index df2ff96..89862fa 100644 >--- a/drivers/gpu/drm/i915/intel_guc_fw.c >+++ b/drivers/gpu/drm/i915/intel_guc_fw.c >@@ -37,7 +37,7 @@ > #define BXT_FW_MINOR 29 > > #define KBL_FW_MAJOR 9 >-#define KBL_FW_MINOR 14 >+#define KBL_FW_MINOR 39 > > #define GLK_FW_MAJOR 10 > #define GLK_FW_MINOR 56 >-- >1.9.1
On Wed, Nov 29, 2017 at 10:22:11PM +0000, Srivatsa, Anusha wrote: > > > >-----Original Message----- > >From: Kamble, Sagar A > >Sent: Wednesday, November 29, 2017 8:19 AM > >To: intel-gfx@lists.freedesktop.org > >Cc: Kamble, Sagar A <sagar.a.kamble@intel.com>; Mcgee, Jeff > ><jeff.mcgee@intel.com>; Spotswood, John A <john.a.spotswood@intel.com>; > >Srivatsa, Anusha <anusha.srivatsa@intel.com>; Wajdeczko, Michal > ><Michal.Wajdeczko@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; Joonas > >Lahtinen <joonas.lahtinen@linux.intel.com> > >Subject: [PATCH v2 3/3] drm/i915/guc: Change default GuC FW for KBL to v9.39 > > > >This patch makes v9.39 firmware as default firmware for KBL. > > > >Note: GuC logging control is changed with this firmware. GuC is expecting i915 to > >set control bit to enable "default logging" > >while using GuC action UK_LOG_ENABLE_LOGGING. > >However i915 is currently not doing this because it is version specific change and > >can be handled entirely in GuC. It will need to be fixed in future firmwares. > > > >This update includes (since v9.14): > > > >- DCC spec changes for BXT + DCT enabling > >- Bug Fix for power conservation feature SLPC_DCC > >- Scheduler 1-element submission during DCC cycles. > >- SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC > >- Moving GuC non_critical r/w data to lower SRAM 64KB > >- Media engine Reset fix. Correctly marking context for resubmission in > > Media Reset case. > >- ABT Disable bug fix. Disabled Evaluation mode on context change. > >- Async FW in Engine Schedule feature (not enabled from KMD) > >- GuC clean up to align developer build in line to production build. > >- Disable ARAT interrupt before programming ARAT delta. > >- Memory range check in Parse to avoid failure due to overflow. > >- GuC Msg Channel Hang WA - Stall GUC for mmio access when IDI is low > > during CPD flow. > >- Fix for submit queue over flow issue > >- Enabling IBC on KBL GT3 15W, GT4 45W > >- Disabling wrong device ID WA in production signed kernel > >- Enabling WA for MSGCH hang issue upto required KBL stepping > >- Clear forcewake in CSB when SQ is empty. > >- 3Tries of GuC2CSME wake request > >- During reset one parameter was not getting accounted > >- Disable DCC 1-elem mode submission > >- Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder. > >- This is file location change.No functional change done as part of this > > check in. > >- Enabling Guc Log changes for ultra low logging for OCA > >- Enabling Dynamic Render Power Well Hysteresis Programming for Compute > > Worklaods > >- Enabling build failure check to catch critical section overflow. > >- Disable build.bat redundant prints. > >- Move few least used functions to non-critical section. > >- Rearrange GuC documentation folder structure. > >- Synchronize SLPC internal debug interface with other branches. > >- Fixing Issue with Default Guc Log changes for OCA using special Control > > Bit > >- Aggressive DCC implementation for supported platforms. > > > >v2: Rebase. Updated commit message. > > > >Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> > >Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> > >Cc: Spotswood John A <john.a.spotswood@intel.com> > >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > >Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > >Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > >Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Reviewed-by: Anusha Srivatsa<anusha.srivatsa@intel.com > Thanks for the patches, thanks for splitting that initial series as requested and thanks for review. All 3 patches merged to dinq. > > > drivers/gpu/drm/i915/intel_guc_fw.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > >diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c > >b/drivers/gpu/drm/i915/intel_guc_fw.c > >index df2ff96..89862fa 100644 > >--- a/drivers/gpu/drm/i915/intel_guc_fw.c > >+++ b/drivers/gpu/drm/i915/intel_guc_fw.c > >@@ -37,7 +37,7 @@ > > #define BXT_FW_MINOR 29 > > > > #define KBL_FW_MAJOR 9 > >-#define KBL_FW_MINOR 14 > >+#define KBL_FW_MINOR 39 > > > > #define GLK_FW_MAJOR 10 > > #define GLK_FW_MINOR 56 > >-- > >1.9.1 >
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index df2ff96..89862fa 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -37,7 +37,7 @@ #define BXT_FW_MINOR 29 #define KBL_FW_MAJOR 9 -#define KBL_FW_MINOR 14 +#define KBL_FW_MINOR 39 #define GLK_FW_MAJOR 10 #define GLK_FW_MINOR 56