From patchwork Thu Dec 7 04:34:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Weinan Z" X-Patchwork-Id: 10097621 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 24C63602BF for ; Thu, 7 Dec 2017 04:41:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1826129B30 for ; Thu, 7 Dec 2017 04:41:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0CB7D29EBD; Thu, 7 Dec 2017 04:41:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 889B329B30 for ; Thu, 7 Dec 2017 04:41:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7546989C9B; Thu, 7 Dec 2017 04:41:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3A24D6E1DC for ; Thu, 7 Dec 2017 04:40:38 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Dec 2017 20:40:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,371,1508828400"; d="scan'208";a="10350201" Received: from weinanli-build.sh.intel.com ([10.239.12.12]) by fmsmga004.fm.intel.com with ESMTP; 06 Dec 2017 20:40:37 -0800 From: Weinan Li To: intel-gfx@lists.freedesktop.org Date: Thu, 7 Dec 2017 12:34:39 +0800 Message-Id: <1512621279-27199-4-git-send-email-weinan.z.li@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1512621279-27199-1-git-send-email-weinan.z.li@intel.com> References: <1512621279-27199-1-git-send-email-weinan.z.li@intel.com> Subject: [Intel-gfx] [PATCH 3/3] drm/i915/gvt: load host render mocs once in mocs switch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Load host render mocs registers once for delta update of mocs switch, it reduces mmio read times obviously, then brings performance improvement during multi-vms switch. Signed-off-by: Weinan Li --- drivers/gpu/drm/i915/gvt/render.c | 51 ++++++++++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index 724f10d..13c3f01 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -141,8 +141,41 @@ struct render_mmio { {RCS, _MMIO(0x20e4), 0xffff, false}, }; -static u32 gen9_render_mocs[I915_NUM_ENGINES][64]; -static u32 gen9_render_mocs_L3[32]; +static struct { + bool initialized; + u32 control_table[I915_NUM_ENGINES][64]; + u32 l3cc_table[32]; +} gen9_render_mocs; + +static int load_render_mocs(struct drm_i915_private *dev_priv) +{ + i915_reg_t offset; + u32 regs[] = { + [RCS] = 0xc800, + [VCS] = 0xc900, + [VCS2] = 0xca00, + [BCS] = 0xcc00, + [VECS] = 0xcb00, + }; + int ring_id, i; + + for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) { + offset.reg = regs[ring_id]; + for (i = 0; i < 64; i++) { + gen9_render_mocs.control_table[ring_id][i] = + I915_READ_FW(offset); + offset.reg += 4; + } + } + + offset.reg = 0xb020; + for (i = 0; i < 32; i++) { + gen9_render_mocs.l3cc_table[i] = + I915_READ_FW(offset); + offset.reg += 4; + } + gen9_render_mocs.initialized = true; +} static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) { @@ -210,18 +243,19 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) return; - offset.reg = regs[ring_id]; + if (!pre && !gen9_render_mocs.initialized) + load_render_mocs(dev_priv); + offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { if (pre) old_v = vgpu_vreg(pre, offset); else - old_v = gen9_render_mocs[ring_id][i] - = I915_READ_FW(offset); + old_v = gen9_render_mocs.control_table[ring_id][i]; if (next) new_v = vgpu_vreg(next, offset); else - new_v = gen9_render_mocs[ring_id][i]; + new_v = gen9_render_mocs.control_table[ring_id][i]; if (old_v != new_v) I915_WRITE_FW(offset, new_v); @@ -235,12 +269,11 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, if (pre) old_v = vgpu_vreg(pre, l3_offset); else - old_v = gen9_render_mocs_L3[i] - = I915_READ_FW(offset); + old_v = gen9_render_mocs.l3cc_table[i]; if (next) new_v = vgpu_vreg(next, l3_offset); else - new_v = gen9_render_mocs_L3[i]; + new_v = gen9_render_mocs.l3cc_table[i]; if (old_v != new_v) I915_WRITE_FW(l3_offset, new_v);