From patchwork Tue Dec 12 02:09:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Weinan Z" X-Patchwork-Id: 10106127 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 12A2360752 for ; Tue, 12 Dec 2017 02:15:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 059972989A for ; Tue, 12 Dec 2017 02:15:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EEAB629A71; Tue, 12 Dec 2017 02:15:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A39BD2989A for ; Tue, 12 Dec 2017 02:15:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 32C986E155; Tue, 12 Dec 2017 02:15:11 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id F30E36E1E0 for ; Tue, 12 Dec 2017 02:15:08 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Dec 2017 18:15:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,393,1508828400"; d="scan'208";a="17460242" Received: from weinanli-build.sh.intel.com ([10.239.12.12]) by orsmga002.jf.intel.com with ESMTP; 11 Dec 2017 18:15:06 -0800 From: Weinan Li To: intel-gfx@lists.freedesktop.org Date: Tue, 12 Dec 2017 10:09:07 +0800 Message-Id: <1513044548-17339-4-git-send-email-weinan.z.li@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1513044548-17339-1-git-send-email-weinan.z.li@intel.com> References: <1513044548-17339-1-git-send-email-weinan.z.li@intel.com> Subject: [Intel-gfx] [PATCH v2 3/4] drm/i915/gvt: refine mocs save restore policy X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Save and restore the mocs regs of one VM in GVT-g burning too much CPU utilization. Add LRI command scan to monitor the change of mocs registers, save the state in vreg, and use delta update policy to restore them. It can obviously reduce the MMIO r/w count, and improve the performance of context switch. Signed-off-by: Weinan Li --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/gvt/mmio_context.c | 33 ++++++++++++++++++--------------- 2 files changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 18c4573..be5c519b 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -825,6 +825,21 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s, return 0; } +static inline bool is_mocs_mmio(unsigned int offset) +{ + return ((offset >= 0xc800) && (offset <= 0xcff8)) || + ((offset >= 0xb020) && (offset <= 0xb0a0)); +} + +static int mocs_cmd_reg_handler(struct parser_exec_state *s, + unsigned int offset, unsigned int index) +{ + if (!is_mocs_mmio(offset)) + return -EINVAL; + vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1); + return 0; +} + static int cmd_reg_handler(struct parser_exec_state *s, unsigned int offset, unsigned int index, char *cmd) { @@ -848,6 +863,10 @@ static int cmd_reg_handler(struct parser_exec_state *s, return 0; } + if (is_mocs_mmio(offset) && + mocs_cmd_reg_handler(s, offset, index)) + return -EINVAL; + if (is_force_nonpriv_mmio(offset) && force_nonpriv_reg_handler(s, offset, index)) return -EPERM; diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 5ad72fc..06ea3d2 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -203,6 +203,8 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, { struct drm_i915_private *dev_priv; i915_reg_t offset, l3_offset; + u32 old_v, new_v; + u32 regs[] = { [RCS] = 0xc800, [VCS] = 0xc900, @@ -220,16 +222,17 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, for (i = 0; i < 64; i++) { if (pre) - vgpu_vreg(pre, offset) = - I915_READ_FW(offset); + old_v = vgpu_vreg(pre, offset); else - gen9_render_mocs[ring_id][i] = - I915_READ_FW(offset); - + old_v = gen9_render_mocs[ring_id][i] + = I915_READ_FW(offset); if (next) - I915_WRITE_FW(offset, vgpu_vreg(next, offset)); + new_v = vgpu_vreg(next, offset); else - I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]); + new_v = gen9_render_mocs[ring_id][i]; + + if (old_v != new_v) + I915_WRITE_FW(offset, new_v); offset.reg += 4; } @@ -238,17 +241,17 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, l3_offset.reg = 0xb020; for (i = 0; i < 32; i++) { if (pre) - vgpu_vreg(pre, l3_offset) = - I915_READ_FW(l3_offset); + old_v = vgpu_vreg(pre, l3_offset); else - gen9_render_mocs_L3[i] = - I915_READ_FW(l3_offset); + old_v = gen9_render_mocs_L3[i] + = I915_READ_FW(offset); if (next) - I915_WRITE_FW(l3_offset, - vgpu_vreg(next, l3_offset)); + new_v = vgpu_vreg(next, l3_offset); else - I915_WRITE_FW(l3_offset, - gen9_render_mocs_L3[i]); + new_v = gen9_render_mocs_L3[i]; + + if (old_v != new_v) + I915_WRITE_FW(l3_offset, new_v); l3_offset.reg += 4; }