From patchwork Mon Dec 18 21:22:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jackie Li X-Patchwork-Id: 10121873 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D34DF60390 for ; Mon, 18 Dec 2017 21:23:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C3CE01FE8A for ; Mon, 18 Dec 2017 21:23:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B71BB200DF; Mon, 18 Dec 2017 21:23:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2A7B51FE8A for ; Mon, 18 Dec 2017 21:23:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 15D8D6E17C; Mon, 18 Dec 2017 21:23:36 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id DB7776E17C for ; Mon, 18 Dec 2017 21:23:34 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Dec 2017 13:23:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,423,1508828400"; d="scan'208";a="185292067" Received: from yli84-z170x-ud5.fm.intel.com ([10.19.83.14]) by orsmga005.jf.intel.com with ESMTP; 18 Dec 2017 13:23:33 -0800 From: Jackie Li To: intel-gfx@lists.freedesktop.org Date: Mon, 18 Dec 2017 13:22:08 -0800 Message-Id: <1513632128-13492-1-git-send-email-yaodong.li@intel.com> X-Mailer: git-send-email 2.7.4 Cc: Ben Widawsky Subject: [Intel-gfx] [RFC] drm/i915: Add a new modparam for customized ring multiplier X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Zhipeng Gong SKL platforms requires a higher ring multiplier when there's massive GPU load. Current driver doesn't provide a way to override the ring multiplier. This patch adds a new module parameter to allow the overriding of ring multiplier for Gen9 platforms. Cc: Ben Widawsky Cc: Chris Wilson Cc: Oscar Mateo Cc: Sagar Arun Kamble Cc: Dmitry Rogozhkin Cc: Zhipeng Gong Signed-off-by: Jackie Li --- drivers/gpu/drm/i915/i915_params.c | 4 +++ drivers/gpu/drm/i915/i915_params.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 57 ++++++++++++++++++++++++++++++++------ 3 files changed, 53 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 8dfea03..f3dd179 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -101,6 +101,10 @@ i915_param_named_unsafe(disable_power_well, int, 0400, "Disable display power wells when possible " "(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)"); +i915_param_named_unsafe(ring_multiplier, uint, 0400, + "Override Ring/GT frequency multiplier." + "(2=2x ring multiplier [defaut], 3=3x ring multiplier)"); + i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)"); i915_param_named(fastboot, bool, 0600, diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 792ce26..6073d1c 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -43,6 +43,7 @@ param(int, enable_ppgtt, -1) \ param(int, enable_psr, -1) \ param(int, disable_power_well, -1) \ + param(unsigned int, ring_multiplier, 2) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ param(int, enable_guc, 0) \ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a349c4f..080051b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6818,6 +6818,34 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv) intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } +static inline void sanitize_ring_multiplier(struct drm_i915_private *i915) +{ + unsigned int m = i915_modparams.ring_multiplier; + + /* Currently, only support 2x or 3x multipliers */ + if (m != 2 && m != 3) + i915_modparams.ring_multiplier = 2; +} + +static inline void get_ring_multiplier(struct drm_i915_private *i915, + unsigned int *numer, + unsigned int *denom) +{ + sanitize_ring_multiplier(i915); + + if (IS_GEN9(i915)) { + *numer = i915_modparams.ring_multiplier; + *denom = 1; + } else if IS_HASWELL(i915) { + *numer = 5; + *denom = 2; + } else { + /* Use a 2x ring multiplier by default */ + *numer = 2; + *denom = 1; + } +} + static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; @@ -6825,6 +6853,8 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) unsigned int gpu_freq; unsigned int max_ia_freq, min_ring_freq; unsigned int max_gpu_freq, min_gpu_freq; + unsigned int ring_mul_numer, ring_mul_denom; + unsigned int ring_request_freq; int scaling_factor = 180; struct cpufreq_policy *policy; @@ -6858,6 +6888,9 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) max_gpu_freq = rps->max_freq; } + + get_ring_multiplier(dev_priv, &ring_mul_numer, &ring_mul_denom); + /* * For each potential GPU frequency, load a ring frequency we'd like * to use for memory access. We do this by specifying the IA frequency @@ -6867,18 +6900,24 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) int diff = max_gpu_freq - gpu_freq; unsigned int ia_freq = 0, ring_freq = 0; + /* + * ring_request_freq = ring_multiplier * GPU frequency. + * Ring freq is in 100MHz units while GPU frequency is in 50MHz + * units. + */ + ring_request_freq = mult_frac(gpu_freq, ring_mul_numer, + 2 * ring_mul_denom); + if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { /* - * ring_freq = 2 * GT. ring_freq is in 100MHz units - * No floor required for ring frequency on SKL. + * ring_freq = ring request freq. No floor required for + * ring frequency on SKL. */ - ring_freq = gpu_freq; - } else if (INTEL_INFO(dev_priv)->gen >= 8) { - /* max(2 * GT, DDR). NB: GT is 50MHz units */ - ring_freq = max(min_ring_freq, gpu_freq); - } else if (IS_HASWELL(dev_priv)) { - ring_freq = mult_frac(gpu_freq, 5, 4); - ring_freq = max(min_ring_freq, ring_freq); + ring_freq = ring_request_freq; + } else if (INTEL_INFO(dev_priv)->gen >= 8 || + IS_HASWELL(dev_priv)) { + /* max(ring request freq, DDR). NB: GT is 50MHz units */ + ring_freq = max(min_ring_freq, ring_request_freq); /* leave ia_freq as the default, chosen by cpufreq */ } else { /* On older processors, there is no separate ring