| Message ID | 1520468038-11503-1-git-send-email-matthew.s.atwood@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hey Matt, Your patch doesn't build. Missing semicolon, dude. On Wed, Mar 07, 2018 at 04:13:58PM -0800, matthew.s.atwood@intel.com wrote: > From: Matt Atwood <matthew.s.atwood@intel.com> > > DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8 > bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended > receiver capabilities. For panels that use this new feature wait interval > would be increased by 512 ms, when spec is max 16 ms. This behavior is > described in table 2-158 of DP 1.4 spec address 0000eh. > > With the introduction of DP 1.4 spec main link clock recovery was > standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value. > > To avoid breaking panels that are not spec compiant we now warn on > invalid values. > > V2: commit title/message, masking all 7 bits, warn on out of spec values. > V3: commit message, make link train clock recovery follow DP 1.4 spec. > V4: style changes > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > --- > drivers/gpu/drm/drm_dp_helper.c | 18 ++++++++++++++---- > include/drm/drm_dp_helper.h | 6 ++++++ > 2 files changed, 20 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index adf79be..6985ff3 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -119,18 +119,28 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI > EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); > > void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { > - if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) > + int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & DP_TRAINING_AUX_RD_MASK; > + > + if (rd_interval > 4) > + DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)", rd_interval); > + > + if (rd_interval == 0 || (dpcd[DP_DPCD_REV] >= DP_REV_14)) > udelay(100); > else > - mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); > + mdelay(rd_interval * 4) Need a semicolon here. /mnt/host/source/src/third_party/kernel/v4.14/drivers/gpu/drm/drm_dp_helper.c: In function 'drm_dp_link_train_clock_recovery_delay': /mnt/host/source/src/third_party/kernel/v4.14/drivers/gpu/drm/drm_dp_helper.c:131:1: error: expected ';' before '}' token } ^ make[4]: *** [/mnt/host/source/src/third_party/kernel/v4.14/scripts/Makefile.build:320: drivers/gpu/drm/drm_dp_helper.o] Error 1 Thanks, Benson
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index adf79be..6985ff3 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -119,18 +119,28 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { - if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) + int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & DP_TRAINING_AUX_RD_MASK; + + if (rd_interval > 4) + DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)", rd_interval); + + if (rd_interval == 0 || (dpcd[DP_DPCD_REV] >= DP_REV_14)) udelay(100); else - mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); + mdelay(rd_interval * 4) } EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { - if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) + int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & DP_TRAINING_AUX_RD_MASK; + + if (rd_interval > 4) + DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)", rd_interval); + + if (rd_interval == 0) udelay(400); else - mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); + mdelay(rd_interval * 4); } EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index da58a42..1269ef8 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -64,6 +64,11 @@ /* AUX CH addresses */ /* DPCD */ #define DP_DPCD_REV 0x000 +# define DP_REV_10 0x10 +# define DP_REV_11 0x11 +# define DP_REV_12 0x12 +# define DP_REV_13 0x13 +# define DP_REV_14 0x14 #define DP_MAX_LINK_RATE 0x001 @@ -118,6 +123,7 @@ # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ +# define DP_TRAINING_AUX_RD_MASK 0x7F /* 1.3 */ #define DP_ADAPTER_CAP 0x00f /* 1.2 */ # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)