From patchwork Fri Mar 30 08:31:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 10317389 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6E7CF60212 for ; Fri, 30 Mar 2018 08:29:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 61F372A565 for ; Fri, 30 Mar 2018 08:29:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5721F2A569; Fri, 30 Mar 2018 08:29:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E5CEA2A565 for ; Fri, 30 Mar 2018 08:29:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 07DE76E84F; Fri, 30 Mar 2018 08:29:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id B4A4B6E85B for ; Fri, 30 Mar 2018 08:28:49 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Mar 2018 01:28:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,380,1517904000"; d="scan'208";a="38104617" Received: from sakamble-desktop.iind.intel.com ([10.223.26.10]) by FMSMGA003.fm.intel.com with ESMTP; 30 Mar 2018 01:28:47 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Fri, 30 Mar 2018 14:01:54 +0530 Message-Id: <1522398722-12161-10-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522398722-12161-1-git-send-email-sagar.a.kamble@intel.com> References: <1522398722-12161-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] [PATCH v12 09/17] drm/i915/guc/slpc: Reset SLPC on engine reset with flag TDR_OCCURRED X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sujaritha Sundaresan MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On engine reset, SLPC needs to be notified for it to clear metrics/stats. This is done by sending GUC_SLPC_EVENT_RESET with a flag GUC_SLPC_RESET_FLAG_TDR_OCCURRED. v2: Full GPU reset in i915 triggers reload of GuC and SLPC reset happens along that path. Hence only handling engine reset. Signed-off-by: Sagar Arun Kamble Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Radoslaw Szwichtenberg Cc: Michal Wajdeczko Cc: Sujaritha Sundaresan Cc: Jeff McGee --- drivers/gpu/drm/i915/i915_irq.c | 3 +++ drivers/gpu/drm/i915/intel_guc_slpc.c | 36 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc_slpc.h | 1 + drivers/gpu/drm/i915/intel_uc.c | 5 +++++ drivers/gpu/drm/i915/intel_uc.h | 1 + 5 files changed, 46 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index cc7dd85..726391c 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3020,6 +3020,9 @@ void i915_handle_error(struct drm_i915_private *dev_priv, wake_up_bit(&dev_priv->gpu_error.flags, I915_RESET_ENGINE + engine->id); } + + if (!engine_mask) + intel_uc_handle_engine_reset(dev_priv); } if (!engine_mask) diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c index 7f75d218..bdafbaa 100644 --- a/drivers/gpu/drm/i915/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/intel_guc_slpc.c @@ -390,6 +390,20 @@ static bool slpc_stopped(struct intel_guc_slpc *slpc) return (data.global_state == SLPC_GLOBAL_STATE_NOT_RUNNING); } +static void host2guc_slpc_tdr_reset(struct intel_guc_slpc *slpc) +{ + struct intel_guc *guc = slpc_to_guc(slpc); + u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma); + struct slpc_event_input data = {0}; + + data.header.value = SLPC_EVENT(SLPC_EVENT_RESET, 3); + data.args[0] = shared_data_gtt_offset; + data.args[1] = 0; + data.args[2] = SLPC_RESET_FLAG_TDR_OCCURRED; + + slpc_send(slpc, &data, 5); +} + /** * intel_guc_slpc_init() - Initialize the SLPC shared data structure. * @slpc: pointer to intel_guc_slpc. @@ -471,6 +485,28 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) } /** + * intel_guc_slpc_handle_engine_reset() - Notify SLPC about engine reset. + * @slpc: pointer to intel_guc_slpc. + * + * On engine reset, SLPC needs to be notified for it to clear metrics/stats. + * This function notifies by invoking SLPC_EVENT_RESET with a flag + * SLPC_RESET_FLAG_TDR_OCCURRED. + */ +void intel_guc_slpc_handle_engine_reset(struct intel_guc_slpc *slpc) +{ + mutex_lock(&slpc->lock); + + host2guc_slpc_tdr_reset(slpc); + + /* Check whether SLPC is running */ + if (wait_for(slpc_running(slpc), 5)) + DRM_ERROR("SLPC not enabled! State = %s\n", + slpc_get_state(slpc)); + + mutex_unlock(&slpc->lock); +} + +/** * intel_guc_slpc_disable() - Stop SLPC tasks. * @slpc: pointer to intel_guc_slpc. * diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h index 87dac07..75f0b5d 100644 --- a/drivers/gpu/drm/i915/intel_guc_slpc.h +++ b/drivers/gpu/drm/i915/intel_guc_slpc.h @@ -16,6 +16,7 @@ struct intel_guc_slpc { int intel_guc_slpc_init(struct intel_guc_slpc *slpc); int intel_guc_slpc_enable(struct intel_guc_slpc *slpc); +void intel_guc_slpc_handle_engine_reset(struct intel_guc_slpc *slpc); void intel_guc_slpc_disable(struct intel_guc_slpc *slpc); void intel_guc_slpc_fini(struct intel_guc_slpc *slpc); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index ece6687..c050444 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -475,6 +475,11 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) return ret; } +void intel_uc_handle_engine_reset(struct drm_i915_private *dev_priv) +{ + intel_guc_slpc_handle_engine_reset(&dev_priv->guc.slpc); +} + void intel_uc_fini_hw(struct drm_i915_private *dev_priv) { struct intel_guc *guc = &dev_priv->guc; diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 76139d3..1d67ad3 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -35,6 +35,7 @@ int intel_uc_init_misc(struct drm_i915_private *dev_priv); void intel_uc_fini_misc(struct drm_i915_private *dev_priv); void intel_uc_sanitize(struct drm_i915_private *dev_priv); int intel_uc_init_hw(struct drm_i915_private *dev_priv); +void intel_uc_handle_engine_reset(struct drm_i915_private *dev_priv); void intel_uc_fini_hw(struct drm_i915_private *dev_priv); int intel_uc_init(struct drm_i915_private *dev_priv); void intel_uc_fini(struct drm_i915_private *dev_priv);