From patchwork Fri Mar 30 08:32:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 10317393 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 367C260467 for ; Fri, 30 Mar 2018 08:29:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 27D8C2A55F for ; Fri, 30 Mar 2018 08:29:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1B4F62A567; Fri, 30 Mar 2018 08:29:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 68CF02A55F for ; Fri, 30 Mar 2018 08:29:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E4B46E857; Fri, 30 Mar 2018 08:29:16 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5766D6E857 for ; Fri, 30 Mar 2018 08:29:06 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Mar 2018 01:29:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,380,1517904000"; d="scan'208";a="38104697" Received: from sakamble-desktop.iind.intel.com ([10.223.26.10]) by FMSMGA003.fm.intel.com with ESMTP; 30 Mar 2018 01:29:03 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Fri, 30 Mar 2018 14:02:00 +0530 Message-Id: <1522398722-12161-16-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522398722-12161-1-git-send-email-sagar.a.kamble@intel.com> References: <1522398722-12161-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] [PATCH v12 15/17] drm/i915/guc/slpc: Add i915_guc_slpc_info to debugfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sujaritha Sundaresan , Tom O'Rourke MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tom O'Rourke i915_guc_slpc_info shows the contents of SLPC shared data parsed into text format. v1: Reformat slpc info (Radek). Squashed query task state info in slpc info, kunmap before seq_print (Paulo) Return void instead of ignored return value (Paulo) Avoid magic numbers and use local variables (Jon Bloomfield). Removed WARN_ON for checking msb of gtt address of shared gem obj. (Chris) Moved definition of power plan and power source to earlier patch in the series. drm/i915/slpc: Allocate/Release/Initialize SLPC shared data (Akash) v2-v3: Rebase. v4: Updated with GuC firmware v9. v5: Updated host2guc_slpc_query_task_state with struct slpc_input_event structure. Removed unnecessary checks of vma from i915_slpc_info. Created helpers for reading the SLPC shared data and string form of SLPC state. (Sagar) v6: s/i915_slpc_info/i915_guc_slpc_info. Prepared helpers platform_sku _to_string, power_plan_to_string and power_source_to_string. (Michal Wajdeczko) v7: Moved all SLPC data printing changes to guc_slpc.c and making use of drm_printer. Signed-off-by: Tom O'Rourke Signed-off-by: Sagar Arun Kamble Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Radoslaw Szwichtenberg Cc: Michal Wajdeczko Cc: Sujaritha Sundaresan Cc: Jeff McGee --- drivers/gpu/drm/i915/i915_debugfs.c | 10 ++ drivers/gpu/drm/i915/intel_guc_slpc.c | 193 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc_slpc.h | 2 + 3 files changed, 205 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f90ad52..1a66507 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1053,6 +1053,15 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, NULL, i915_next_seqno_set, "0x%llx\n"); +static int i915_guc_slpc_info(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_guc_slpc *slpc = &dev_priv->guc.slpc; + struct drm_printer p = drm_seq_file_printer(m); + + return intel_guc_slpc_info(slpc, &p); +} + static int i915_frequency_info(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -5097,6 +5106,7 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1}, {"i915_guc_stage_pool", i915_guc_stage_pool, 0}, {"i915_guc_slpc_params", i915_guc_slpc_params_info, 0}, + {"i915_guc_slpc_info", i915_guc_slpc_info, 0}, {"i915_huc_load_status", i915_huc_load_status_info, 0}, {"i915_frequency_info", i915_frequency_info, 0}, {"i915_hangcheck_info", i915_hangcheck_info, 0}, diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c index 7bd5e3e..94c6c19 100644 --- a/drivers/gpu/drm/i915/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/intel_guc_slpc.c @@ -487,6 +487,199 @@ static void slpc_get_param(struct intel_guc_slpc *slpc, u32 id, kunmap_atomic(data); } +static const char *slpc_platform_sku_stringify(int platform_sku) +{ + const char *str = NULL; + + switch (platform_sku) { + case SLPC_PLATFORM_SKU_UNDEFINED: + str = "undefined"; + break; + case SLPC_PLATFORM_SKU_ULX: + str = "ULX"; + break; + case SLPC_PLATFORM_SKU_ULT: + str = "ULT"; + break; + case SLPC_PLATFORM_SKU_T: + str = "T"; + break; + case SLPC_PLATFORM_SKU_MOBL: + str = "Mobile"; + break; + case SLPC_PLATFORM_SKU_DT: + str = "DT"; + break; + case SLPC_PLATFORM_SKU_UNKNOWN: + default: + str = "unknown"; + break; + } + + return str; +} + +static const char *slpc_power_plan_stringify(int power_plan) +{ + const char *str = NULL; + + switch (power_plan) { + case SLPC_POWER_PLAN_UNDEFINED: + str = "undefined"; + break; + case SLPC_POWER_PLAN_BATTERY_SAVER: + str = "battery saver"; + break; + case SLPC_POWER_PLAN_BALANCED: + str = "balanced"; + break; + case SLPC_POWER_PLAN_PERFORMANCE: + str = "performance"; + break; + case SLPC_POWER_PLAN_UNKNOWN: + default: + str = "unknown"; + break; + } + + return str; +} + +static const char *slpc_power_source_stringify(int power_source) +{ + const char *str = NULL; + + switch (power_source) { + case SLPC_POWER_SOURCE_UNDEFINED: + str = "undefined"; + break; + case SLPC_POWER_SOURCE_AC: + str = "AC"; + break; + case SLPC_POWER_SOURCE_DC: + str = "DC"; + break; + case SLPC_POWER_SOURCE_UNKNOWN: + default: + str = "unknown"; + break; + } + + return str; +} + +int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p) +{ + struct intel_guc *guc = slpc_to_guc(slpc); + struct drm_i915_private *dev_priv = guc_to_i915(guc); + struct slpc_shared_data data; + struct slpc_platform_info *platform_info; + struct slpc_task_state_data *task_data; + int i, value; + + if (!USES_GUC_SLPC(dev_priv)) + return -ENODEV; + + GEM_BUG_ON(!slpc->vma); + + intel_runtime_pm_get(dev_priv); + mutex_lock(&slpc->lock); + + slpc_read_shared_data(slpc, &data); + + mutex_unlock(&slpc->lock); + intel_runtime_pm_put(dev_priv); + + platform_info = &data.platform_info; + + drm_printf(p, "shared data size: %d\n", data.shared_data_size); + + value = data.global_state; + drm_printf(p, "global state: %d (", value); + drm_printf(p, "%s)\n", slpc_state_stringify(value)); + + value = platform_info->sku; + drm_printf(p, "sku: %d (%s)\n", + value, slpc_platform_sku_stringify(value)); + drm_printf(p, "slice count: %d\n", platform_info->slice_count); + + value = SLPC_POWER_PLAN(platform_info->power_plan_source); + drm_printf(p, "power plan/source: 0x%x\n\tplan:\t%s", + platform_info->power_plan_source, + slpc_power_plan_stringify(value)); + + value = SLPC_POWER_SOURCE(platform_info->power_plan_source); + drm_printf(p, "\n\tsource:\t%s\n", + slpc_power_source_stringify(value)); + + drm_printf(p, + "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\t" + "Pe: %d\n\tPn: %d\n", + platform_info->p0_freq * 50, + platform_info->p1_freq * 50, + platform_info->pe_freq * 50, + platform_info->pn_freq * 50); + + task_data = &data.task_state_data; + drm_printf(p, "task state data: 0x%08x 0x%08x\n", + task_data->bitfield1, task_data->bitfield2); + + drm_printf(p, "\tgtperf task active: %s\n", + yesno(task_data->gtperf_task_active)); + drm_printf(p, "\tgtperf stall possible: %s\n", + yesno(task_data->gtperf_stall_possible)); + drm_printf(p, "\tgtperf gaming mode: %s\n", + yesno(task_data->gtperf_gaming_mode)); + drm_printf(p, "\tgtperf target fps: %d\n", + task_data->gtperf_target_fps); + + drm_printf(p, "\tdcc task active: %s\n", + yesno(task_data->dcc_task_active)); + drm_printf(p, "\tin dcc: %s\n", + yesno(task_data->in_dcc)); + drm_printf(p, "\tin dct: %s\n", + yesno(task_data->in_dct)); + drm_printf(p, "\tfreq switch active: %s\n", + yesno(task_data->freq_switch_active)); + + drm_printf(p, "\tibc enabled: %s\n", + yesno(task_data->ibc_enabled)); + drm_printf(p, "\tibc active: %s\n", + yesno(task_data->ibc_active)); + drm_printf(p, "\tpg1 enabled: %s\n", + yesno(task_data->pg1_enabled)); + drm_printf(p, "\tpg1 active: %s\n", + yesno(task_data->pg1_active)); + + drm_printf(p, "\tunslice max freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->max_unslice_freq * GEN9_FREQ_SCALER)); + drm_printf(p, "\tunslice min freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->min_unslice_freq * GEN9_FREQ_SCALER)); + drm_printf(p, "\tslice max freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->max_slice_freq * GEN9_FREQ_SCALER)); + drm_printf(p, "\tslice min freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->min_slice_freq * GEN9_FREQ_SCALER)); + + drm_printf(p, "override parameter bitfield\n"); + for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++) + drm_printf(p, "%d: 0x%08x\n", i, + data.override_params_set_bits[i]); + + drm_printf(p, "override parameters (only non-zero shown)\n"); + for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) { + value = data.override_params_values[i]; + if (value) + drm_printf(p, "%d: 0x%8x\n", i, value); + } + + return 0; +} + + /** * intel_guc_slpc_task_control() - Update status of SLPC task. * @slpc: pointer to intel_guc_slpc. diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h index 693343e..edb0dec 100644 --- a/drivers/gpu/drm/i915/intel_guc_slpc.h +++ b/drivers/gpu/drm/i915/intel_guc_slpc.h @@ -41,6 +41,8 @@ void intel_guc_slpc_params_print(struct intel_guc_slpc *slpc, int intel_guc_slpc_param_control(struct intel_guc_slpc *slpc, u32 params, u32 op, u32 id, u32 value); +int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p); + int intel_guc_slpc_init(struct intel_guc_slpc *slpc); int intel_guc_slpc_enable(struct intel_guc_slpc *slpc); int intel_guc_slpc_max_freq_set(struct intel_guc_slpc *slpc, u32 val);