diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f90ad52..1a66507 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1053,6 +1053,15 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 			NULL, i915_next_seqno_set,
 			"0x%llx\n");
 
+static int i915_guc_slpc_info(struct seq_file *m, void *unused)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_guc_slpc *slpc = &dev_priv->guc.slpc;
+	struct drm_printer p = drm_seq_file_printer(m);
+
+	return intel_guc_slpc_info(slpc, &p);
+}
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5097,6 +5106,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
 	{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
 	{"i915_guc_slpc_params", i915_guc_slpc_params_info, 0},
+	{"i915_guc_slpc_info", i915_guc_slpc_info, 0},
 	{"i915_huc_load_status", i915_huc_load_status_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.c b/drivers/gpu/drm/i915/intel_guc_slpc.c
index 7bd5e3e..94c6c19 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.c
@@ -487,6 +487,199 @@ static void slpc_get_param(struct intel_guc_slpc *slpc, u32 id,
 	kunmap_atomic(data);
 }
 
+static const char *slpc_platform_sku_stringify(int platform_sku)
+{
+	const char *str = NULL;
+
+	switch (platform_sku) {
+	case SLPC_PLATFORM_SKU_UNDEFINED:
+		str = "undefined";
+		break;
+	case SLPC_PLATFORM_SKU_ULX:
+		str = "ULX";
+		break;
+	case SLPC_PLATFORM_SKU_ULT:
+		str = "ULT";
+		break;
+	case SLPC_PLATFORM_SKU_T:
+		str = "T";
+		break;
+	case SLPC_PLATFORM_SKU_MOBL:
+		str = "Mobile";
+		break;
+	case SLPC_PLATFORM_SKU_DT:
+		str = "DT";
+		break;
+	case SLPC_PLATFORM_SKU_UNKNOWN:
+	default:
+		str = "unknown";
+		break;
+	}
+
+	return str;
+}
+
+static const char *slpc_power_plan_stringify(int power_plan)
+{
+	const char *str = NULL;
+
+	switch (power_plan) {
+	case SLPC_POWER_PLAN_UNDEFINED:
+		str = "undefined";
+		break;
+	case SLPC_POWER_PLAN_BATTERY_SAVER:
+		str = "battery saver";
+		break;
+	case SLPC_POWER_PLAN_BALANCED:
+		str = "balanced";
+		break;
+	case SLPC_POWER_PLAN_PERFORMANCE:
+		str = "performance";
+		break;
+	case SLPC_POWER_PLAN_UNKNOWN:
+	default:
+		str = "unknown";
+		break;
+	}
+
+	return str;
+}
+
+static const char *slpc_power_source_stringify(int power_source)
+{
+	const char *str = NULL;
+
+	switch (power_source) {
+	case SLPC_POWER_SOURCE_UNDEFINED:
+		str = "undefined";
+		break;
+	case SLPC_POWER_SOURCE_AC:
+		str = "AC";
+		break;
+	case SLPC_POWER_SOURCE_DC:
+		str = "DC";
+		break;
+	case SLPC_POWER_SOURCE_UNKNOWN:
+	default:
+		str = "unknown";
+		break;
+	}
+
+	return str;
+}
+
+int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	struct slpc_shared_data data;
+	struct slpc_platform_info *platform_info;
+	struct slpc_task_state_data *task_data;
+	int i, value;
+
+	if (!USES_GUC_SLPC(dev_priv))
+		return -ENODEV;
+
+	GEM_BUG_ON(!slpc->vma);
+
+	intel_runtime_pm_get(dev_priv);
+	mutex_lock(&slpc->lock);
+
+	slpc_read_shared_data(slpc, &data);
+
+	mutex_unlock(&slpc->lock);
+	intel_runtime_pm_put(dev_priv);
+
+	platform_info = &data.platform_info;
+
+	drm_printf(p, "shared data size: %d\n", data.shared_data_size);
+
+	value = data.global_state;
+	drm_printf(p, "global state: %d (", value);
+	drm_printf(p, "%s)\n", slpc_state_stringify(value));
+
+	value = platform_info->sku;
+	drm_printf(p, "sku: %d (%s)\n",
+		   value, slpc_platform_sku_stringify(value));
+	drm_printf(p, "slice count: %d\n", platform_info->slice_count);
+
+	value = SLPC_POWER_PLAN(platform_info->power_plan_source);
+	drm_printf(p, "power plan/source: 0x%x\n\tplan:\t%s",
+		   platform_info->power_plan_source,
+		   slpc_power_plan_stringify(value));
+
+	value = SLPC_POWER_SOURCE(platform_info->power_plan_source);
+	drm_printf(p, "\n\tsource:\t%s\n",
+		   slpc_power_source_stringify(value));
+
+	drm_printf(p,
+		   "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\t"
+		   "Pe: %d\n\tPn: %d\n",
+		   platform_info->p0_freq * 50,
+		   platform_info->p1_freq * 50,
+		   platform_info->pe_freq * 50,
+		   platform_info->pn_freq * 50);
+
+	task_data = &data.task_state_data;
+	drm_printf(p, "task state data: 0x%08x 0x%08x\n",
+		   task_data->bitfield1, task_data->bitfield2);
+
+	drm_printf(p, "\tgtperf task active: %s\n",
+		   yesno(task_data->gtperf_task_active));
+	drm_printf(p, "\tgtperf stall possible: %s\n",
+		   yesno(task_data->gtperf_stall_possible));
+	drm_printf(p, "\tgtperf gaming mode: %s\n",
+		   yesno(task_data->gtperf_gaming_mode));
+	drm_printf(p, "\tgtperf target fps: %d\n",
+		   task_data->gtperf_target_fps);
+
+	drm_printf(p, "\tdcc task active: %s\n",
+		   yesno(task_data->dcc_task_active));
+	drm_printf(p, "\tin dcc: %s\n",
+		   yesno(task_data->in_dcc));
+	drm_printf(p, "\tin dct: %s\n",
+		   yesno(task_data->in_dct));
+	drm_printf(p, "\tfreq switch active: %s\n",
+		   yesno(task_data->freq_switch_active));
+
+	drm_printf(p, "\tibc enabled: %s\n",
+		   yesno(task_data->ibc_enabled));
+	drm_printf(p, "\tibc active: %s\n",
+		   yesno(task_data->ibc_active));
+	drm_printf(p, "\tpg1 enabled: %s\n",
+		   yesno(task_data->pg1_enabled));
+	drm_printf(p, "\tpg1 active: %s\n",
+		   yesno(task_data->pg1_active));
+
+	drm_printf(p, "\tunslice max freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->max_unslice_freq * GEN9_FREQ_SCALER));
+	drm_printf(p, "\tunslice min freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->min_unslice_freq * GEN9_FREQ_SCALER));
+	drm_printf(p, "\tslice max freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->max_slice_freq * GEN9_FREQ_SCALER));
+	drm_printf(p, "\tslice min freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->min_slice_freq * GEN9_FREQ_SCALER));
+
+	drm_printf(p, "override parameter bitfield\n");
+	for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+		drm_printf(p, "%d: 0x%08x\n", i,
+			   data.override_params_set_bits[i]);
+
+	drm_printf(p, "override parameters (only non-zero shown)\n");
+	for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+		value = data.override_params_values[i];
+		if (value)
+			drm_printf(p, "%d: 0x%8x\n", i, value);
+	}
+
+	return 0;
+}
+
+
 /**
  * intel_guc_slpc_task_control() - Update status of SLPC task.
  * @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h
index 693343e..edb0dec 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/intel_guc_slpc.h
@@ -41,6 +41,8 @@ void intel_guc_slpc_params_print(struct intel_guc_slpc *slpc,
 int intel_guc_slpc_param_control(struct intel_guc_slpc *slpc,
 				 u32 params, u32 op, u32 id, u32 value);
 
+int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p);
+
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_max_freq_set(struct intel_guc_slpc *slpc, u32 val);
