From patchwork Fri Mar 30 08:31:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 10317373 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9A48860212 for ; Fri, 30 Mar 2018 08:28:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E3352A565 for ; Fri, 30 Mar 2018 08:28:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 82F7B2A567; Fri, 30 Mar 2018 08:28:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 09BB52A565 for ; Fri, 30 Mar 2018 08:28:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B8666E854; Fri, 30 Mar 2018 08:28:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id C0FC16E84E for ; Fri, 30 Mar 2018 08:28:28 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Mar 2018 01:28:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,380,1517904000"; d="scan'208";a="38104543" Received: from sakamble-desktop.iind.intel.com ([10.223.26.10]) by FMSMGA003.fm.intel.com with ESMTP; 30 Mar 2018 01:28:26 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Fri, 30 Mar 2018 14:01:47 +0530 Message-Id: <1522398722-12161-3-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522398722-12161-1-git-send-email-sagar.a.kamble@intel.com> References: <1522398722-12161-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] [PATCH v12 02/17] drm/i915/guc/slpc: Disable host RPS X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sujaritha Sundaresan MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On platforms with GuC SLPC enabled, we need to ensure Host RPS functions don't update HW RPS state that will be controlled by GuC SLPC then. Host RPS functions are now gated by either USES_GUC_SLPC() or rps->enabled checks. If SLPC is enabled following functions will be bypassed 1. gpu_ips_init 2. intel_enable|disable_rps 3. rps portion of sanitize_gt_powersave gen6_rps_irq_handler, rps_work, gen6_set_rps should not get invoked hence GEM_BUG_ON(USES_GUC_SLPC()) is added in those functions. We continue to use the state setup by intel_init_gt_powersave as i915 will be configuring min/max frequency limits. Signed-off-by: Sagar Arun Kamble Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Radoslaw Szwichtenberg Cc: Michal Wajdeczko Cc: Sujaritha Sundaresan Cc: Jeff McGee --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++------ drivers/gpu/drm/i915/i915_sysfs.c | 5 +++-- drivers/gpu/drm/i915/intel_pm.c | 26 +++++++++++++++++++++++++- 4 files changed, 41 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 800230b..5176801 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2599,6 +2599,7 @@ intel_info(const struct drm_i915_private *dev_priv) #define USES_GUC(dev_priv) intel_uc_is_using_guc() #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission() #define USES_HUC(dev_priv) intel_uc_is_using_huc() +#define USES_GUC_SLPC(dev_priv) intel_uc_is_using_guc_slpc() #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 27aee25..cc7dd85 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1192,6 +1192,8 @@ static void gen6_pm_rps_work(struct work_struct *work) int new_delay, adj, min, max; u32 pm_iir = 0; + GEM_BUG_ON(USES_GUC_SLPC(dev_priv)); + spin_lock_irq(&dev_priv->irq_lock); if (rps->interrupts_enabled) { pm_iir = fetch_and_zero(&rps->pm_iir); @@ -1742,6 +1744,8 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) struct intel_rps *rps = &dev_priv->gt_pm.rps; if (pm_iir & dev_priv->pm_rps_events) { + GEM_BUG_ON(USES_GUC_SLPC(dev_priv)); + spin_lock(&dev_priv->irq_lock); gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); if (rps->interrupts_enabled) { @@ -4256,12 +4260,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (HAS_GUC_SCHED(dev_priv)) dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT; - /* Let's track the enabled rps events */ - if (IS_VALLEYVIEW(dev_priv)) - /* WaGsvRC0ResidencyMethod:vlv */ - dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; - else - dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; + if (!USES_GUC_SLPC(dev_priv)) { + /* Let's track the enabled rps events */ + if (IS_VALLEYVIEW(dev_priv)) + /* WaGsvRC0ResidencyMethod:vlv */ + dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; + else + dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; + } rps->pm_intrmsk_mbz = 0; diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index e5e6f6b..c3083fa 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -322,9 +322,10 @@ static ssize_t gt_boost_freq_mhz_store(struct device *kdev, rps->boost_freq = val; boost = atomic_read(&rps->num_waiters); } - mutex_unlock(&dev_priv->pcu_lock); - if (boost) + + if (boost && rps->enabled) schedule_work(&rps->work); + mutex_unlock(&dev_priv->pcu_lock); return count; } diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 19e82aa..51bc147e9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6215,6 +6215,8 @@ static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val) { struct intel_rps *rps = &dev_priv->gt_pm.rps; + GEM_BUG_ON(USES_GUC_SLPC(dev_priv)); + /* min/max delay may still have been modified so be sure to * write the limits value. */ @@ -6310,6 +6312,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; + if (USES_GUC_SLPC(dev_priv)) + return; + mutex_lock(&dev_priv->pcu_lock); if (rps->enabled) { u8 freq; @@ -6340,6 +6345,9 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; + if (USES_GUC_SLPC(dev_priv)) + return; + /* Flush our bottom-half so that it does not race with us * setting the idle frequency and so that it is bounded by * our rpm wakeref. And then disable the interrupts to stop any @@ -6367,6 +6375,9 @@ void gen6_rps_boost(struct i915_request *rq, unsigned long flags; bool boost; + if (USES_GUC_SLPC(dev_priv)) + return; + /* This is intentionally racy! We peek at the state here, then * validate inside the RPS worker. */ @@ -7855,6 +7866,9 @@ ips_ping_for_i915_load(void) void intel_gpu_ips_init(struct drm_i915_private *dev_priv) { + if (USES_GUC_SLPC(dev_priv)) + return; + /* We only register the i915 ips part with intel-ips once everything is * set up, to avoid intel-ips sneaking in and reading bogus values. */ spin_lock_irq(&mchdev_lock); @@ -8024,10 +8038,14 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv) void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) { - dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */ + if (!USES_GUC_SLPC(dev_priv)) + dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */ dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */ intel_disable_gt_powersave(dev_priv); + if (USES_GUC_SLPC(dev_priv)) + return; + if (INTEL_GEN(dev_priv) < 11) gen6_reset_rps_interrupts(dev_priv); else @@ -8069,6 +8087,9 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv) { lockdep_assert_held(&dev_priv->pcu_lock); + if (USES_GUC_SLPC(dev_priv)) + return; + if (!dev_priv->gt_pm.rps.enabled) return; @@ -8135,6 +8156,9 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; + if (USES_GUC_SLPC(dev_priv)) + return; + lockdep_assert_held(&dev_priv->pcu_lock); if (rps->enabled)