From patchwork Fri Mar 30 08:31:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 10317379 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 37AF260467 for ; Fri, 30 Mar 2018 08:28:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2A8C72A566 for ; Fri, 30 Mar 2018 08:28:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1EC132A569; Fri, 30 Mar 2018 08:28:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8DD8B2A566 for ; Fri, 30 Mar 2018 08:28:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F0F426E85B; Fri, 30 Mar 2018 08:28:51 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 24D0F6E85A for ; Fri, 30 Mar 2018 08:28:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Mar 2018 01:28:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,380,1517904000"; d="scan'208";a="38104567" Received: from sakamble-desktop.iind.intel.com ([10.223.26.10]) by FMSMGA003.fm.intel.com with ESMTP; 30 Mar 2018 01:28:34 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Fri, 30 Mar 2018 14:01:50 +0530 Message-Id: <1522398722-12161-6-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522398722-12161-1-git-send-email-sagar.a.kamble@intel.com> References: <1522398722-12161-1-git-send-email-sagar.a.kamble@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v12 05/17] drm/i915/guc/slpc: Add SLPC communication interfaces X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sujaritha Sundaresan , Tom O'Rourke Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Communication with SLPC is via Host to GuC interrupt through shared data and parameters. This patch defines the structure of shared data, parameters, data structure to be passed as input and received as output from SLPC. This patch also defines the events to be sent as input and status values output by GuC on processing SLPC events. SLPC shared data has details of SKU type, Slice count, IA Perf MSR values, SLPC state, Power source/plan, SLPC tasks status. Parameters allow overriding task control, frequency range etc. v1: fix whitespace (Sagar) v2-v3: Rebase. v4: Updated with GuC firmware v9. v5: Added definition of input and output data structures for SLPC events. Updated commit message. v6: Removed definition of host2guc_slpc. Will be added in the next patch that uses it. Commit subject update. Rebase. v7: Added definition of SLPC_RESET_FLAG_TDR_OCCURRED to be sent throgh SLPC reset in case of engine reset. Moved all Host/SLPC interfaces from later patches to this patch. Commit message update. v8: Updated value of SLPC_RESET_FLAG_TDR_OCCURRED. v9: Removed struct slpc_param, slpc_paramlist and corresponding defines. Will be added in later patches where they are used. v10: Rebase. Prepared separate header for SLPC firmware interface. Signed-off-by: Tom O'Rourke Signed-off-by: Sagar Arun Kamble Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Radoslaw Szwichtenberg Cc: Michal Wajdeczko Cc: Sujaritha Sundaresan Cc: Jeff McGee --- drivers/gpu/drm/i915/intel_guc_slpc.h | 2 + drivers/gpu/drm/i915/intel_guc_slpc_fwif.h | 211 +++++++++++++++++++++++++++++ 2 files changed, 213 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_guc_slpc_fwif.h diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h b/drivers/gpu/drm/i915/intel_guc_slpc.h index 66c76fe..81250c0 100644 --- a/drivers/gpu/drm/i915/intel_guc_slpc.h +++ b/drivers/gpu/drm/i915/intel_guc_slpc.h @@ -6,6 +6,8 @@ #ifndef _INTEL_GUC_SLPC_H_ #define _INTEL_GUC_SLPC_H_ +#include + struct intel_guc_slpc { }; diff --git a/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h new file mode 100644 index 0000000..9400af4 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_guc_slpc_fwif.h @@ -0,0 +1,211 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2015-2018 Intel Corporation + */ +#ifndef _INTEL_GUC_SLPC_FWIF_H_ +#define _INTEL_GUC_SLPC_FWIF_H_ + +#include + +enum slpc_status { + SLPC_STATUS_OK = 0, + SLPC_STATUS_ERROR = 1, + SLPC_STATUS_ILLEGAL_COMMAND = 2, + SLPC_STATUS_INVALID_ARGS = 3, + SLPC_STATUS_INVALID_PARAMS = 4, + SLPC_STATUS_INVALID_DATA = 5, + SLPC_STATUS_OUT_OF_RANGE = 6, + SLPC_STATUS_NOT_SUPPORTED = 7, + SLPC_STATUS_NOT_IMPLEMENTED = 8, + SLPC_STATUS_NO_DATA = 9, + SLPC_STATUS_EVENT_NOT_REGISTERED = 10, + SLPC_STATUS_REGISTER_LOCKED = 11, + SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12, + SLPC_STATUS_VALUE_ALREADY_SET = 13, + SLPC_STATUS_VALUE_ALREADY_UNSET = 14, + SLPC_STATUS_VALUE_NOT_CHANGED = 15, + SLPC_STATUS_MEMIO_ERROR = 16, + SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17, + SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18, + SLPC_STATUS_NO_EVENT_QUEUED = 19, + SLPC_STATUS_OUT_OF_SPACE = 20, + SLPC_STATUS_TIMEOUT = 21, + SLPC_STATUS_NO_LOCK = 22, + SLPC_STATUS_MAX +}; + +enum slpc_event_id { + SLPC_EVENT_RESET = 0, + SLPC_EVENT_SHUTDOWN = 1, + SLPC_EVENT_PLATFORM_INFO_CHANGE = 2, + SLPC_EVENT_DISPLAY_MODE_CHANGE = 3, + SLPC_EVENT_FLIP_COMPLETE = 4, + SLPC_EVENT_QUERY_TASK_STATE = 5, + SLPC_EVENT_PARAMETER_SET = 6, + SLPC_EVENT_PARAMETER_UNSET = 7, +}; + +enum slpc_param_id { + SLPC_PARAM_TASK_ENABLE_GTPERF = 0, + SLPC_PARAM_TASK_DISABLE_GTPERF = 1, + SLPC_PARAM_TASK_ENABLE_BALANCER = 2, + SLPC_PARAM_TASK_DISABLE_BALANCER = 3, + SLPC_PARAM_TASK_ENABLE_DCC = 4, + SLPC_PARAM_TASK_DISABLE_DCC = 5, + SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6, + SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7, + SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8, + SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9, + SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10, + SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11, + SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12, + SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13, + SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14, + SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15, + SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16, + SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17, + SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18, + SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19, + SLPC_MAX_PARAM, + SLPC_KMD_MAX_PARAM = 32, +}; + +enum slpc_global_state { + SLPC_GLOBAL_STATE_NOT_RUNNING = 0, + SLPC_GLOBAL_STATE_INITIALIZING = 1, + SLPC_GLOBAL_STATE_RESETTING = 2, + SLPC_GLOBAL_STATE_RUNNING = 3, + SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4, + SLPC_GLOBAL_STATE_ERROR = 5 +}; + +enum slpc_platform_sku { + SLPC_PLATFORM_SKU_UNDEFINED = 0, + SLPC_PLATFORM_SKU_ULX = 1, + SLPC_PLATFORM_SKU_ULT = 2, + SLPC_PLATFORM_SKU_T = 3, + SLPC_PLATFORM_SKU_MOBL = 4, + SLPC_PLATFORM_SKU_DT = 5, + SLPC_PLATFORM_SKU_UNKNOWN = 6, +}; + +enum slpc_power_source { + SLPC_POWER_SOURCE_UNDEFINED = 0, + SLPC_POWER_SOURCE_AC = 1, + SLPC_POWER_SOURCE_DC = 2, + SLPC_POWER_SOURCE_UNKNOWN = 3, +}; + +enum slpc_power_plan { + SLPC_POWER_PLAN_UNDEFINED = 0, + SLPC_POWER_PLAN_BATTERY_SAVER = 1, + SLPC_POWER_PLAN_BALANCED = 2, + SLPC_POWER_PLAN_PERFORMANCE = 3, + SLPC_POWER_PLAN_UNKNOWN = 4, +}; + +struct slpc_platform_info { + u8 sku; + u8 slice_count; + u8 reserved; + u8 power_plan_source; + u8 p0_freq; + u8 p1_freq; + u8 pe_freq; + u8 pn_freq; + u32 reserved1; + u32 reserved2; +} __packed; + +struct slpc_task_state_data { + union { + u32 bitfield1; + struct { + u32 gtperf_task_active:1; + u32 gtperf_stall_possible:1; + u32 gtperf_gaming_mode:1; + u32 gtperf_target_fps:8; + u32 dcc_task_active:1; + u32 in_dcc:1; + u32 in_dct:1; + u32 freq_switch_active:1; + u32 ibc_enabled:1; + u32 ibc_active:1; + u32 pg1_enabled:1; + u32 pg1_active:1; + u32 reserved:13; + }; + }; + union { + u32 bitfield2; + struct { + u32 max_unslice_freq:8; + u32 min_unslice_freq:8; + u32 max_slice_freq:8; + u32 min_slice_freq:8; + }; + }; +} __packed; + +#define SLPC_MAX_OVERRIDE_PARAMETERS 192 +#define SLPC_OVERRIDE_BITFIELD_SIZE \ + ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32) + +struct slpc_shared_data { + u32 reserved; + u32 shared_data_size; + u32 global_state; + struct slpc_platform_info platform_info; + struct slpc_task_state_data task_state_data; + u32 override_params_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE]; + u32 override_params_values[SLPC_MAX_OVERRIDE_PARAMETERS]; +} __packed; + +enum slpc_reset_flags { + SLPC_RESET_FLAG_TDR_OCCURRED = (1 << 0) +}; + +#define SLPC_EVENT_MAX_INPUT_ARGS 7 +#define SLPC_EVENT_MAX_OUTPUT_ARGS 1 + +union slpc_event_input_header { + u32 value; + struct { + u32 num_args:8; + u32 event_id:8; + }; +}; + +struct slpc_event_input { + u32 h2g_action_id; + union slpc_event_input_header header; + u32 args[SLPC_EVENT_MAX_INPUT_ARGS]; +} __packed; + +union slpc_event_output_header { + u32 value; + struct { + u32 num_args:8; + u32 event_id:8; + u32 status:16; + }; +}; + +struct slpc_event_output { + u32 reserved; + union slpc_event_output_header header; + u32 args[SLPC_EVENT_MAX_OUTPUT_ARGS]; +} __packed; + +#define SLPC_EVENT(id, argc) ((u32)(id) << 8 | (argc)) +#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6)) +#define SLPC_POWER_PLAN(plan_source) ((plan_source) & 0x3F) +#define SLPC_POWER_SOURCE(plan_source) ((plan_source) >> 6) + +#define SLPC_PARAM_TASK_DEFAULT 0 +#define SLPC_PARAM_TASK_ENABLED 1 +#define SLPC_PARAM_TASK_DISABLED 2 +#define SLPC_PARAM_TASK_UNKNOWN 3 + +#endif