| Message ID | 1543311548-19149-2-git-send-email-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ICL DSI PLL enable | expand |
On Tue, 27 Nov 2018, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > From: Madhav Chauhan <madhav.chauhan@intel.com> > > This patch calculates various DPLL dividers and > parameters for DSI encoder and adjust AFE clock > for DSI. For DSI, 8x clock is AFE clock. > > v2: Extend haswell_crtc_compute_clock() for Gen11 DSI > > v3: Rebase > > v4: use port clock instead of bitrate. > > v5: Reabse and remove divide by 5 > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 4 +++- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++--- > 2 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 27bdf91..1318faf 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9303,10 +9303,12 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv) > static int haswell_crtc_compute_clock(struct intel_crtc *crtc, > struct intel_crtc_state *crtc_state) > { > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > struct intel_atomic_state *state = > to_intel_atomic_state(crtc_state->base.state); > > - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { > + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) || > + IS_ICELAKE(dev_priv)) { > struct intel_encoder *encoder = > intel_get_crtc_new_encoder(state, crtc_state); > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 901e150..e3cb0db 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -2523,10 +2523,10 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, > > if (intel_port_is_tc(dev_priv, encoder->port)) > ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params); > - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params); > - else > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) I think this breaks EDP and DP MST. Probably just safest to add || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) alongside the HDMI branch. BR, Jani. > ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params); > + else > + ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params); > > if (!ret) > return false;
> -----Original Message----- > From: Kulkarni, Vandita > Sent: Tuesday, November 27, 2018 3:09 PM > To: intel-gfx@lists.freedesktop.org > Cc: Chauhan, Madhav <madhav.chauhan@intel.com>; Nikula, Jani > <jani.nikula@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Kulkarni, > Vandita <vandita.kulkarni@intel.com> > Subject: [PATCH 1/6] drm/i915/icl: Calculate DPLL params for DSI > > From: Madhav Chauhan <madhav.chauhan@intel.com> > > This patch calculates various DPLL dividers and parameters for DSI encoder > and adjust AFE clock for DSI. For DSI, 8x clock is AFE clock. > > v2: Extend haswell_crtc_compute_clock() for Gen11 DSI > > v3: Rebase > > v4: use port clock instead of bitrate. > > v5: Reabse and remove divide by 5 > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 4 +++- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++--- > 2 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 27bdf91..1318faf 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9303,10 +9303,12 @@ void hsw_disable_pc8(struct drm_i915_private > *dev_priv) static int haswell_crtc_compute_clock(struct intel_crtc *crtc, > struct intel_crtc_state *crtc_state) { > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > struct intel_atomic_state *state = > to_intel_atomic_state(crtc_state->base.state); > > - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { > + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) || > + IS_ICELAKE(dev_priv)) { Please align IS_ICELAKE(dev_priv) to "(". Regards, Madhav > struct intel_encoder *encoder = > intel_get_crtc_new_encoder(state, crtc_state); > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 901e150..e3cb0db 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -2523,10 +2523,10 @@ static bool icl_calc_dpll_state(struct > intel_crtc_state *crtc_state, > > if (intel_port_is_tc(dev_priv, encoder->port)) > ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params); > - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > - ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params); > - else > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) > ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params); > + else > + ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params); > > if (!ret) > return false; > -- > 1.9.1
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 27bdf91..1318faf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9303,10 +9303,12 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv) static int haswell_crtc_compute_clock(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state) { + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state); - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) || + IS_ICELAKE(dev_priv)) { struct intel_encoder *encoder = intel_get_crtc_new_encoder(state, crtc_state); diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 901e150..e3cb0db 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2523,10 +2523,10 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, if (intel_port_is_tc(dev_priv, encoder->port)) ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params); - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params); - else + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params); + else + ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params); if (!ret) return false;