| Message ID | 1543311548-19149-5-git-send-email-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ICL DSI PLL enable | expand |
On Tue, Nov 27, 2018 at 03:09:06PM +0530, Vandita Kulkarni wrote: > From: Madhav Chauhan <madhav.chauhan@intel.com> > > As per BSPEC, depending on the DSI transcoder being used, > DDI clock for the associated port should be gated. This > patch does the same. > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/icl_dsi.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c > index ec22b2e..fe4efc7 100644 > --- a/drivers/gpu/drm/i915/icl_dsi.c > +++ b/drivers/gpu/drm/i915/icl_dsi.c > @@ -536,6 +536,23 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) > } > } > > +static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > + u32 tmp; > + enum port port; > + > + mutex_lock(&dev_priv->dpll_lock); > + tmp = I915_READ(DPCLKA_CFGCR0_ICL); > + for_each_dsi_port(port, intel_dsi->ports) { > + tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port); > + } > + > + I915_WRITE(DPCLKA_CFGCR0_ICL, tmp); > + mutex_unlock(&dev_priv->dpll_lock); > +} > + > static void > gen11_dsi_configure_transcoder(struct intel_encoder *encoder, > const struct intel_crtc_state *pipe_config) > @@ -883,6 +900,9 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder) > > /* Step (4h, 4i, 4j, 4k): Configure transcoder */ > gen11_dsi_configure_transcoder(encoder, pipe_config); > + > + /* Step 4l: Gate DDI clocks */ > + gen11_dsi_gate_clocks(encoder); I think the default case should be that DDI clocks are gated and here we shouldn't do anything. The DDI clocks will get then ungated only when enabling a DDI encoder in icl_map_plls_to_ports(). There we should also make sure we don't ungate the clock for a DSI encoder. I also have a patch to sanity check the clock gating wrt. DSI too during HW readout, will send that today. > } > > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, Nov 27, 2018 at 04:06:43PM +0200, Imre Deak wrote: > On Tue, Nov 27, 2018 at 03:09:06PM +0530, Vandita Kulkarni wrote: > > From: Madhav Chauhan <madhav.chauhan@intel.com> > > > > As per BSPEC, depending on the DSI transcoder being used, > > DDI clock for the associated port should be gated. This > > patch does the same. > > > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > --- > > drivers/gpu/drm/i915/icl_dsi.c | 20 ++++++++++++++++++++ > > 1 file changed, 20 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c > > index ec22b2e..fe4efc7 100644 > > --- a/drivers/gpu/drm/i915/icl_dsi.c > > +++ b/drivers/gpu/drm/i915/icl_dsi.c > > @@ -536,6 +536,23 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) > > } > > } > > > > +static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) > > +{ > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > + u32 tmp; > > + enum port port; > > + > > + mutex_lock(&dev_priv->dpll_lock); > > + tmp = I915_READ(DPCLKA_CFGCR0_ICL); > > + for_each_dsi_port(port, intel_dsi->ports) { > > + tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port); > > + } > > + > > + I915_WRITE(DPCLKA_CFGCR0_ICL, tmp); > > + mutex_unlock(&dev_priv->dpll_lock); > > +} > > + > > static void > > gen11_dsi_configure_transcoder(struct intel_encoder *encoder, > > const struct intel_crtc_state *pipe_config) > > @@ -883,6 +900,9 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder) > > > > /* Step (4h, 4i, 4j, 4k): Configure transcoder */ > > gen11_dsi_configure_transcoder(encoder, pipe_config); > > + > > + /* Step 4l: Gate DDI clocks */ > > + gen11_dsi_gate_clocks(encoder); > > I think the default case should be that DDI clocks are gated and here we > shouldn't do anything. > > The DDI clocks will get then ungated only when enabling a DDI encoder in > icl_map_plls_to_ports(). Err, scratch the above. Reading the spec again and trying it on a DSI machine it seems we do have to keep the DDI clock ungated up to this point. So that's fine, we just have to make sure not to ungate/gate it also in icl_map_plls_to_ports/icl_unmap_plls_to_ports. > There we should also make sure we don't ungate the clock for a DSI > encoder. > > I also have a patch to sanity check the clock gating wrt. DSI too during > HW readout, will send that today. > > > } > > > > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index ec22b2e..fe4efc7 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -536,6 +536,23 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) } } +static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + u32 tmp; + enum port port; + + mutex_lock(&dev_priv->dpll_lock); + tmp = I915_READ(DPCLKA_CFGCR0_ICL); + for_each_dsi_port(port, intel_dsi->ports) { + tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port); + } + + I915_WRITE(DPCLKA_CFGCR0_ICL, tmp); + mutex_unlock(&dev_priv->dpll_lock); +} + static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) @@ -883,6 +900,9 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder) /* Step (4h, 4i, 4j, 4k): Configure transcoder */ gen11_dsi_configure_transcoder(encoder, pipe_config); + + /* Step 4l: Gate DDI clocks */ + gen11_dsi_gate_clocks(encoder); } static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)