From patchwork Mon Dec 3 07:35:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Zhang, Tina" X-Patchwork-Id: 10708677 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5EA6C14BD for ; Mon, 3 Dec 2018 07:40:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 523C62ACBB for ; Mon, 3 Dec 2018 07:40:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4696B2ACC3; Mon, 3 Dec 2018 07:40:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D32762ACD0 for ; Mon, 3 Dec 2018 07:40:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9CA0C89CD3; Mon, 3 Dec 2018 07:40:52 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id EC4F389AB5; Mon, 3 Dec 2018 07:40:50 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Dec 2018 23:40:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,309,1539673200"; d="scan'208";a="126550083" Received: from tinazhang-linux-1.bj.intel.com ([10.238.158.97]) by fmsmga001.fm.intel.com with ESMTP; 02 Dec 2018 23:40:49 -0800 From: Tina Zhang To: Date: Mon, 3 Dec 2018 15:35:16 +0800 Message-Id: <1543822522-3413-2-git-send-email-tina.zhang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543822522-3413-1-git-send-email-tina.zhang@intel.com> References: <1543822522-3413-1-git-send-email-tina.zhang@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC PATCH 1/7] drm/i915: Introduce meta framebuffer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, kalyan.kondapally@intel.com, intel-gvt-dev@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Meta framebuffer, as a special intel_framebuffer, is used to describe an intel_framebuffer which is already pinned to the GGTT space and can be accessed by the display engine HW. In the virtualization world, with the help of GVT-g, vGPUs can share the entire global GTT space and be able to pin their framebuffers to the global GTT space. However, vGPUs cannot be able to access the display HW registers which are fully controlled by host i915. In order to support the vGPU local display direct flip feature, which is the vGPU can have several assigned display planes and can post its framebuffers to those assigned planes, host i915 must program the display plane registers on behalf of the vGPU. However, without the knowledge of the vGPU's framebuffers, host i915 cannot program those plane registers correctly. To fill this gap, the meta framebuffer is introduced. The meta framebuffer is used by host i915 to describe the framebuffer pinned to the GGTT space by guest OS. Signed-off-by: Tina Zhang Signed-off-by: Zhi Wang Cc: Ville Syrjälä Cc: Daniel Vetter --- drivers/gpu/drm/i915/intel_drv.h | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_sprite.c | 19 ++++++++++++++++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f575ba2..6cf345c 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -187,6 +187,12 @@ enum intel_output_type { #define INTEL_DSI_VIDEO_MODE 0 #define INTEL_DSI_COMMAND_MODE 1 + +enum { + INTEL_META_FB_VGPU = 1, + INTEL_META_FB_MAX, +}; + struct intel_framebuffer { struct drm_framebuffer base; struct intel_rotation_info rot_info; @@ -200,6 +206,15 @@ struct intel_framebuffer { unsigned int x, y; unsigned int pitch; /* pixels */ } rotated[2]; + + struct { + u32 type_id; + u32 ggtt_offset; + void *private; + void (*update)(struct intel_framebuffer *intel_fb, + enum pipe pipe, enum plane_id plane_id); + bool should_be_offscreen; + } meta_fb; }; struct intel_fbdev { diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index abe1938..16a0a5d4 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -486,9 +486,26 @@ skl_program_plane(struct intel_plane *plane, uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; struct intel_plane *linked = plane_state->linked_plane; const struct drm_framebuffer *fb = plane_state->base.fb; + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); u8 alpha = plane_state->base.alpha >> 8; unsigned long irqflags; u32 keymsk, keymax; + u32 offset; + + if (intel_fb->meta_fb.type_id == INTEL_META_FB_VGPU) { + + if (!intel_fb->meta_fb.update) + return; + + intel_fb->meta_fb.update(intel_fb, pipe, plane_id); + + if (intel_fb->meta_fb.should_be_offscreen) + return; + + offset = intel_fb->meta_fb.ggtt_offset; + } else { + offset = intel_plane_ggtt_offset(plane_state); + } /* Sizes are 0 based */ src_w--; @@ -558,7 +575,7 @@ skl_program_plane(struct intel_plane *plane, I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); I915_WRITE_FW(PLANE_SURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + surf_addr); + offset + surf_addr); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); }