From patchwork Mon Dec 3 07:35:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tina" X-Patchwork-Id: 10708687 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4F07B14BD for ; Mon, 3 Dec 2018 07:41:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4075F2AC85 for ; Mon, 3 Dec 2018 07:41:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 34A352ACCC; Mon, 3 Dec 2018 07:41:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D389D2AC96 for ; Mon, 3 Dec 2018 07:41:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B24D89D49; Mon, 3 Dec 2018 07:41:00 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 39EB589CFA; Mon, 3 Dec 2018 07:40:59 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Dec 2018 23:40:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,309,1539673200"; d="scan'208";a="126550102" Received: from tinazhang-linux-1.bj.intel.com ([10.238.158.97]) by fmsmga001.fm.intel.com with ESMTP; 02 Dec 2018 23:40:57 -0800 From: Tina Zhang To: Date: Mon, 3 Dec 2018 15:35:21 +0800 Message-Id: <1543822522-3413-7-git-send-email-tina.zhang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543822522-3413-1-git-send-email-tina.zhang@intel.com> References: <1543822522-3413-1-git-send-email-tina.zhang@intel.com> Subject: [Intel-gfx] [RFC PATCH 6/7] drm/i915/gvt: Enable guest direct page flip X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, kalyan.kondapally@intel.com, intel-gvt-dev@lists.freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Use the vGPU direct plane flip framework do the guest direct page flip. Signed-off-by: Tina Zhang Cc: Zhenyu Wang Cc: Zhi Wang --- drivers/gpu/drm/i915/gvt/handlers.c | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index b5475c9..89a22a5 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -743,6 +743,35 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, return 0; } +static int handle_vgpu_page_flip(struct intel_vgpu *vgpu, int pipe, + enum plane_id plane) +{ + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + struct intel_vgpu_plane_info vgpu_plane_info; + u32 vgpu_id = vgpu->id; + u32 pipe_id = pipe; + u32 plane_id = plane; + u32 vgpu_plane_id = (vgpu_id << 16) | (pipe_id << 8) | plane_id; + + if (plane == PLANE_CURSOR) { + DRM_DEBUG_KMS("Assigning CURSOR plane hasn't been supported\n"); + } else { /* primary plane and sprite plane */ + vgpu_plane_info.id = vgpu_plane_id; + vgpu_plane_info.plane = PLANE_PRIMARY; + vgpu_plane_info.offset = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & + I915_GTT_PAGE_MASK; + vgpu_plane_info.stride = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & 0x3ff; + vgpu_plane_info.control = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); + vgpu_plane_info.size = vgpu_vreg_t(vgpu, DSPSIZE(pipe)); + vgpu_plane_info.plane_offset = vgpu_vreg_t(vgpu, DSPOFFSET(pipe)); + vgpu_plane_info.vgpu = vgpu; + } + + intel_vgpu_plane_update(vgpu->gvt, &vgpu_plane_info); + + return 0; +} + #define DSPSURF_TO_PIPE(offset) \ calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) @@ -761,6 +790,8 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, write_vreg(vgpu, offset, p_data, bytes); vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); + handle_vgpu_page_flip(vgpu, index, PLANE_PRIMARY); + set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); return 0; } @@ -768,10 +799,15 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, #define SPRSURF_TO_PIPE(offset) \ calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) +#define SPRSURF_TO_PLANE(offset, pipe) \ + calc_index(offset, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe), \ + _PLANE_SURF_3(pipe), PLANE_SURF(PIPE_C, PLANE_CURSOR)) + static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { unsigned int index = SPRSURF_TO_PIPE(offset); + unsigned int plane = SPRSURF_TO_PLANE(offset, index); i915_reg_t surflive_reg = SPRSURFLIVE(index); int flip_event[] = { [PIPE_A] = SPRITE_A_FLIP_DONE, @@ -782,6 +818,8 @@ static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, write_vreg(vgpu, offset, p_data, bytes); vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); + handle_vgpu_page_flip(vgpu, index, plane); + set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); return 0; }