| Message ID | 1553256832-15257-1-git-send-email-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] drm/i915/icl: Ungate ddi clocks before IO enable | expand |
On Fri, Mar 22, 2019 at 05:43:51PM +0530, Vandita Kulkarni wrote: > IO enable sequencing needs ddi clocks enabled. > These clocks will be gated at a later point in > the enable sequence. > > v2: Fix the commit header (uma) > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > Reviewed-by: Uma Shankar <uma.shankar@intel.com> > --- > drivers/gpu/drm/i915/icl_dsi.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c > index beb30d9..6a5b9fa 100644 > --- a/drivers/gpu/drm/i915/icl_dsi.c > +++ b/drivers/gpu/drm/i915/icl_dsi.c > @@ -589,6 +589,13 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, > val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); > } > I915_WRITE(DPCLKA_CFGCR0_ICL, val); > + > + val = I915_READ(DPCLKA_CFGCR0_ICL); This read looks totally redundant. > + for_each_dsi_port(port, intel_dsi->ports) { > + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); > + } > + I915_WRITE(DPCLKA_CFGCR0_ICL, val); > + > POSTING_READ(DPCLKA_CFGCR0_ICL); > > mutex_unlock(&dev_priv->dpll_lock); > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> -----Original Message----- > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > Sent: Friday, March 22, 2019 8:03 PM > To: Kulkarni, Vandita <vandita.kulkarni@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com> > Subject: Re: [Intel-gfx] [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO enable > > On Fri, Mar 22, 2019 at 05:43:51PM +0530, Vandita Kulkarni wrote: > > IO enable sequencing needs ddi clocks enabled. > > These clocks will be gated at a later point in the enable sequence. > > > > v2: Fix the commit header (uma) > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > Reviewed-by: Uma Shankar <uma.shankar@intel.com> > > --- > > drivers/gpu/drm/i915/icl_dsi.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c > > b/drivers/gpu/drm/i915/icl_dsi.c index beb30d9..6a5b9fa 100644 > > --- a/drivers/gpu/drm/i915/icl_dsi.c > > +++ b/drivers/gpu/drm/i915/icl_dsi.c > > @@ -589,6 +589,13 @@ static void gen11_dsi_map_pll(struct intel_encoder > *encoder, > > val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); > > } > > I915_WRITE(DPCLKA_CFGCR0_ICL, val); > > + > > + val = I915_READ(DPCLKA_CFGCR0_ICL); > > This read looks totally redundant. Yes, it should have written what is in val already. thanks for the review. Will remove it. Regards, Vandita > > > + for_each_dsi_port(port, intel_dsi->ports) { > > + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); > > + } > > + I915_WRITE(DPCLKA_CFGCR0_ICL, val); > > + > > POSTING_READ(DPCLKA_CFGCR0_ICL); > > > > mutex_unlock(&dev_priv->dpll_lock); > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index beb30d9..6a5b9fa 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -589,6 +589,13 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); } I915_WRITE(DPCLKA_CFGCR0_ICL, val); + + val = I915_READ(DPCLKA_CFGCR0_ICL); + for_each_dsi_port(port, intel_dsi->ports) { + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); + } + I915_WRITE(DPCLKA_CFGCR0_ICL, val); + POSTING_READ(DPCLKA_CFGCR0_ICL); mutex_unlock(&dev_priv->dpll_lock);