Message ID | 1553513202-13863-1-git-send-email-vandita.kulkarni@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v3,1/2] drm/i915/icl: Ungate ddi clocks before IO enable | expand |
On Mon, 25 Mar 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > IO enable sequencing needs ddi clocks enabled. > These clocks will be gated at a later point in > the enable sequence. > > v2: Fix the commit header (Uma) > v3: Remove the redundant read (Ville) > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > Reviewed-by: Uma Shankar <uma.shankar@intel.com> Fixes: 949fc52af19e ("drm/i915/icl: add pll mapping for DSI") Both patches look fine, I'll merge once we get a positive CI result (I queued a re-test), BR, Jani. > --- > drivers/gpu/drm/i915/icl_dsi.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c > index 92440ff..4aef5dd 100644 > --- a/drivers/gpu/drm/i915/icl_dsi.c > +++ b/drivers/gpu/drm/i915/icl_dsi.c > @@ -589,6 +589,12 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, > val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); > } > I915_WRITE(DPCLKA_CFGCR0_ICL, val); > + > + for_each_dsi_port(port, intel_dsi->ports) { > + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); > + } > + I915_WRITE(DPCLKA_CFGCR0_ICL, val); > + > POSTING_READ(DPCLKA_CFGCR0_ICL); > > mutex_unlock(&dev_priv->dpll_lock);
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 92440ff..4aef5dd 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -589,6 +589,12 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); } I915_WRITE(DPCLKA_CFGCR0_ICL, val); + + for_each_dsi_port(port, intel_dsi->ports) { + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); + } + I915_WRITE(DPCLKA_CFGCR0_ICL, val); + POSTING_READ(DPCLKA_CFGCR0_ICL); mutex_unlock(&dev_priv->dpll_lock);