From patchwork Thu Apr 4 08:06:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kulkarni, Vandita" X-Patchwork-Id: 10885255 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 399C617E1 for ; Thu, 4 Apr 2019 08:26:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25F6824603 for ; Thu, 4 Apr 2019 08:26:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 19D89285DD; Thu, 4 Apr 2019 08:26:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B46DF24603 for ; Thu, 4 Apr 2019 08:26:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B5C56E9DC; Thu, 4 Apr 2019 08:26:35 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9CE2B6E9DD for ; Thu, 4 Apr 2019 08:26:34 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Apr 2019 01:26:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,306,1549958400"; d="scan'208";a="220454015" Received: from vandita-desktop.iind.intel.com ([10.223.74.201]) by orsmga001.jf.intel.com with ESMTP; 04 Apr 2019 01:26:33 -0700 From: Vandita Kulkarni To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Apr 2019 13:36:25 +0530 Message-Id: <1554365187-30575-2-git-send-email-vandita.kulkarni@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1554365187-30575-1-git-send-email-vandita.kulkarni@intel.com> References: <1554365187-30575-1-git-send-email-vandita.kulkarni@intel.com> Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Fix pipe config timing mismatch warnings X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Mipi dsi programs the transcoder timings as part of encoder enable sequence, with dual link or single link in consideration. Hence add get transcoder timings as part of the encoder's get_config function. Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 51 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 3 ++- 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index b67ffaa..db6bc3d 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -1176,6 +1176,56 @@ static void gen11_dsi_disable(struct intel_encoder *encoder, gen11_dsi_disable_io_power(encoder); } +static void gen11_dsi_get_timings(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + struct drm_display_mode *adjusted_mode = + &pipe_config->base.adjusted_mode; + /* get config for dsi0 transcoder only */ + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; + /* horizontal timings */ + u16 htotal, hactive, hsync_start, hsync_end; + u32 tmp; + + tmp = I915_READ(HTOTAL(cpu_transcoder)); + hactive = (tmp & 0xffff) + 1; + htotal = ((tmp >> 16) & 0xffff) + 1; + if (intel_dsi->dual_link) { + hactive *= 2; + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) + hactive -= intel_dsi->pixel_overlap; + htotal *= 2; + } + adjusted_mode->crtc_hdisplay = hactive; + adjusted_mode->crtc_htotal = htotal; + adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; + adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; + + tmp = I915_READ(HSYNC(cpu_transcoder)); + hsync_start = (tmp & 0xffff) + 1; + hsync_end = ((tmp >> 16) & 0xffff) + 1; + if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { + if (intel_dsi->dual_link) { + hsync_start *= 2; + hsync_end *= 2; + } + } + adjusted_mode->crtc_hsync_start = hsync_start; + adjusted_mode->crtc_hsync_end = hsync_end; + + tmp = I915_READ(VTOTAL(cpu_transcoder)); + adjusted_mode->crtc_vdisplay = (tmp & 0xffff) + 1; + adjusted_mode->crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; + adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; + adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; + + tmp = I915_READ(VSYNC(cpu_transcoder)); + adjusted_mode->crtc_vsync_start = (tmp & 0xffff) + 1; + adjusted_mode->crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; +} + static void gen11_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { @@ -1186,6 +1236,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; + gen11_dsi_get_timings(encoder, pipe_config); pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7ecfb7d..9f7e4f7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9965,8 +9965,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || INTEL_GEN(dev_priv) >= 11) { haswell_get_ddi_port_state(crtc, pipe_config); - intel_get_pipe_timings(crtc, pipe_config); } + if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) + intel_get_pipe_timings(crtc, pipe_config); intel_get_pipe_src_size(crtc, pipe_config); intel_get_crtc_ycbcr_config(crtc, pipe_config);