| Message ID | 1554365187-30575-3-git-send-email-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix mipi dsi pipe_config mismatch for icl | expand |
Hi Vandita,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v5.1-rc3 next-20190404]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Fix-mipi-dsi-pipe_config-mismatch-for-icl/20190404-192608
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
sparse warnings: (new ones prefixed by >>)
include/uapi/linux/perf_event.h:147:56: sparse: cast truncates bits from constant value (8000000000000000 becomes 0)
drivers/gpu/drm/i915/icl_dsi.c:129:33: sparse: expression using sizeof(void)
>> drivers/gpu/drm/i915/icl_dsi.c:1230:1: sparse: symbol 'gen11_dsi_get_pixel_fmt' was not declared. Should it be static?
Please review and possibly fold the followup patch.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
On Thu, 04 Apr 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > Read back the pixel fomrat register and get the bpp. > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/icl_dsi.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c > index db6bc3d..69cd6b2 100644 > --- a/drivers/gpu/drm/i915/icl_dsi.c > +++ b/drivers/gpu/drm/i915/icl_dsi.c > @@ -1226,6 +1226,30 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, > adjusted_mode->crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; > } > > +enum mipi_dsi_pixel_format > +gen11_dsi_get_pixel_fmt(struct drm_i915_private *dev_priv, > + struct intel_crtc_state *pipe_config) > +{ > + u32 tmp; > + /* get config for dsi0 transcoder only */ > + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; > + > + tmp = I915_READ(DSI_TRANS_FUNC_CONF(cpu_transcoder)); > + tmp &= PIX_FMT_MASK; > + > + switch (tmp) { > + default: > + case PIX_FMT_RGB565: > + return MIPI_DSI_FMT_RGB565; > + case PIX_FMT_RGB666_PACKED: > + return MIPI_DSI_FMT_RGB666_PACKED; > + case PIX_FMT_RGB666_LOOSE: > + return MIPI_DSI_FMT_RGB666; > + case PIX_FMT_RGB888: > + return MIPI_DSI_FMT_RGB888; > + } > +} > + > static void gen11_dsi_get_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > @@ -1238,6 +1262,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, > pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; > gen11_dsi_get_timings(encoder, pipe_config); > pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); > + pipe_config->pipe_bpp = mipi_dsi_pixel_format_to_bpp > + (gen11_dsi_get_pixel_fmt(dev_priv, > + pipe_config)); Please see how this is done for VLV DSI. It now uses PIPEMISC for this. I'd like the two to be the same. BR, Jani. > } > > static int gen11_dsi_compute_config(struct intel_encoder *encoder, > @@ -1253,6 +1280,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder, > struct drm_display_mode *adjusted_mode = > &pipe_config->base.adjusted_mode; > > + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; > intel_fixed_panel_mode(fixed_mode, adjusted_mode); > intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index db6bc3d..69cd6b2 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -1226,6 +1226,30 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, adjusted_mode->crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; } +enum mipi_dsi_pixel_format +gen11_dsi_get_pixel_fmt(struct drm_i915_private *dev_priv, + struct intel_crtc_state *pipe_config) +{ + u32 tmp; + /* get config for dsi0 transcoder only */ + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; + + tmp = I915_READ(DSI_TRANS_FUNC_CONF(cpu_transcoder)); + tmp &= PIX_FMT_MASK; + + switch (tmp) { + default: + case PIX_FMT_RGB565: + return MIPI_DSI_FMT_RGB565; + case PIX_FMT_RGB666_PACKED: + return MIPI_DSI_FMT_RGB666_PACKED; + case PIX_FMT_RGB666_LOOSE: + return MIPI_DSI_FMT_RGB666; + case PIX_FMT_RGB888: + return MIPI_DSI_FMT_RGB888; + } +} + static void gen11_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { @@ -1238,6 +1262,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; gen11_dsi_get_timings(encoder, pipe_config); pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); + pipe_config->pipe_bpp = mipi_dsi_pixel_format_to_bpp + (gen11_dsi_get_pixel_fmt(dev_priv, + pipe_config)); } static int gen11_dsi_compute_config(struct intel_encoder *encoder, @@ -1253,6 +1280,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder, struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; intel_fixed_panel_mode(fixed_mode, adjusted_mode); intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
Read back the pixel fomrat register and get the bpp. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/icl_dsi.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)