diff mbox series

[v3,4/4] drm/i915: Fix pixel clock and crtc clock config mismatch

Message ID 1556778847-7796-4-git-send-email-vandita.kulkarni@intel.com (mailing list archive)
State New, archived
Headers show
Series [v3,1/4] drm/i915: Fix the pipe state timing mismatch warnings | expand

Commit Message

Kulkarni, Vandita May 2, 2019, 6:34 a.m. UTC 
In case of dual link mode, the mode clock that we get
from the VBT is halved.

v2: Simplify the calculation (Jani).

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index cd6a4f3..46b3d30 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1232,7 +1232,11 @@  static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
 	pipe_config->port_clock =
 		cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
+
 	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+	if (intel_dsi->dual_link)
+		pipe_config->base.adjusted_mode.crtc_clock *= 2;
+
 	gen11_dsi_get_timings(encoder, pipe_config);
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);