| Message ID | 1556809862-31203-1-git-send-email-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v5,1/4] drm/i915: Fix the pipe state timing mismatch warnings | expand |
On Thu, 02 May 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > Adjust the get transcoder timings for mipi dsi as per the > set timing calculations. > > v2: Use the existing intel_get_pipe_timings and do the dsi > specific adjustments in the encoder get_config hook.(Ville, Jani) > > v3: Exclude VBLANK and HBLANK registers for dsi transcoder. > > v4: Fix the incomplete conditional logic. > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Pushed the series, thanks for the patches. BR, Jani. > --- > drivers/gpu/drm/i915/icl_dsi.c | 29 +++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++++++------ > 2 files changed, 45 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c > index c6ecc00..45fe69c 100644 > --- a/drivers/gpu/drm/i915/icl_dsi.c > +++ b/drivers/gpu/drm/i915/icl_dsi.c > @@ -1194,6 +1194,34 @@ static void gen11_dsi_disable(struct intel_encoder *encoder, > gen11_dsi_disable_io_power(encoder); > } > > +static void gen11_dsi_get_timings(struct intel_encoder *encoder, > + struct intel_crtc_state *pipe_config) > +{ > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > + struct drm_display_mode *adjusted_mode = > + &pipe_config->base.adjusted_mode; > + > + if (intel_dsi->dual_link) { > + adjusted_mode->crtc_hdisplay *= 2; > + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) > + adjusted_mode->crtc_hdisplay -= > + intel_dsi->pixel_overlap; > + adjusted_mode->crtc_htotal *= 2; > + } > + adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; > + adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; > + > + if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { > + if (intel_dsi->dual_link) { > + adjusted_mode->crtc_hsync_start *= 2; > + adjusted_mode->crtc_hsync_end *= 2; > + } > + } > + adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; > + adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; > + > +} > + > static void gen11_dsi_get_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > @@ -1204,6 +1232,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, > pipe_config->port_clock = > cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); > pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; > + gen11_dsi_get_timings(encoder, pipe_config); > pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); > } > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index dd65d7c..c8cfddc 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -7736,9 +7736,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc, > tmp = I915_READ(HTOTAL(cpu_transcoder)); > pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; > pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; > - tmp = I915_READ(HBLANK(cpu_transcoder)); > - pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; > - pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; > + > + if (!transcoder_is_dsi(cpu_transcoder)) { > + tmp = I915_READ(HBLANK(cpu_transcoder)); > + pipe_config->base.adjusted_mode.crtc_hblank_start = > + (tmp & 0xffff) + 1; > + pipe_config->base.adjusted_mode.crtc_hblank_end = > + ((tmp >> 16) & 0xffff) + 1; > + } > tmp = I915_READ(HSYNC(cpu_transcoder)); > pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; > pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; > @@ -7746,9 +7751,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc, > tmp = I915_READ(VTOTAL(cpu_transcoder)); > pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; > pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; > - tmp = I915_READ(VBLANK(cpu_transcoder)); > - pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; > - pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; > + > + if (!transcoder_is_dsi(cpu_transcoder)) { > + tmp = I915_READ(VBLANK(cpu_transcoder)); > + pipe_config->base.adjusted_mode.crtc_vblank_start = > + (tmp & 0xffff) + 1; > + pipe_config->base.adjusted_mode.crtc_vblank_end = > + ((tmp >> 16) & 0xffff) + 1; > + } > tmp = I915_READ(VSYNC(cpu_transcoder)); > pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; > pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index c6ecc00..45fe69c 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -1194,6 +1194,34 @@ static void gen11_dsi_disable(struct intel_encoder *encoder, gen11_dsi_disable_io_power(encoder); } +static void gen11_dsi_get_timings(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + struct drm_display_mode *adjusted_mode = + &pipe_config->base.adjusted_mode; + + if (intel_dsi->dual_link) { + adjusted_mode->crtc_hdisplay *= 2; + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) + adjusted_mode->crtc_hdisplay -= + intel_dsi->pixel_overlap; + adjusted_mode->crtc_htotal *= 2; + } + adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; + adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; + + if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { + if (intel_dsi->dual_link) { + adjusted_mode->crtc_hsync_start *= 2; + adjusted_mode->crtc_hsync_end *= 2; + } + } + adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; + adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; + +} + static void gen11_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { @@ -1204,6 +1232,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; + gen11_dsi_get_timings(encoder, pipe_config); pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index dd65d7c..c8cfddc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7736,9 +7736,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc, tmp = I915_READ(HTOTAL(cpu_transcoder)); pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; - tmp = I915_READ(HBLANK(cpu_transcoder)); - pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; - pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; + + if (!transcoder_is_dsi(cpu_transcoder)) { + tmp = I915_READ(HBLANK(cpu_transcoder)); + pipe_config->base.adjusted_mode.crtc_hblank_start = + (tmp & 0xffff) + 1; + pipe_config->base.adjusted_mode.crtc_hblank_end = + ((tmp >> 16) & 0xffff) + 1; + } tmp = I915_READ(HSYNC(cpu_transcoder)); pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; @@ -7746,9 +7751,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc, tmp = I915_READ(VTOTAL(cpu_transcoder)); pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; - tmp = I915_READ(VBLANK(cpu_transcoder)); - pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; - pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; + + if (!transcoder_is_dsi(cpu_transcoder)) { + tmp = I915_READ(VBLANK(cpu_transcoder)); + pipe_config->base.adjusted_mode.crtc_vblank_start = + (tmp & 0xffff) + 1; + pipe_config->base.adjusted_mode.crtc_vblank_end = + ((tmp >> 16) & 0xffff) + 1; + } tmp = I915_READ(VSYNC(cpu_transcoder)); pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
Adjust the get transcoder timings for mipi dsi as per the set timing calculations. v2: Use the existing intel_get_pipe_timings and do the dsi specific adjustments in the encoder get_config hook.(Ville, Jani) v3: Exclude VBLANK and HBLANK registers for dsi transcoder. v4: Fix the incomplete conditional logic. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/icl_dsi.c | 29 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++++++------ 2 files changed, 45 insertions(+), 6 deletions(-)