diff mbox series

[34/59] drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI

Message ID 1593552491-23698-35-git-send-email-anitha.chrisanthus@intel.com (mailing list archive)
State New, archived
Headers show
Series Add support for Keem Bay DRM driver | expand

Commit Message

Chrisanthus, Anitha June 30, 2020, 9:27 p.m. UTC 
Enable clocks for LCD, mipi common and mipi tx0
Renamed MSS_CAM_CLK_CTRL and also fixed bug in the
call to set this register.

Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
---
 drivers/gpu/drm/kmb/kmb_drv.c  |  8 ++++----
 drivers/gpu/drm/kmb/kmb_drv.h  | 14 ++++++++++++++
 drivers/gpu/drm/kmb/kmb_dsi.c  |  6 ++++--
 drivers/gpu/drm/kmb/kmb_regs.h |  7 ++++++-
 4 files changed, 28 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c
index 48c2b28..4eb472b 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.c
+++ b/drivers/gpu/drm/kmb/kmb_drv.c
@@ -261,6 +261,9 @@  static int kmb_load(struct drm_device *drm, unsigned long flags)
 		DRM_INFO("Get clk_mipi_cfg after set = %ld\n", clk);
 	}
 
+	/* enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */
+	kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, LCD | MIPI_COMMON |
+			MIPI_TX0);
 #ifdef WIP
 	/* Register irqs here - section 17.3 in databook
 	 * lists LCD at 79 and 82 for MIPI under MSS CPU -
@@ -312,10 +315,7 @@  static int kmb_load(struct drm_device *drm, unsigned long flags)
 
 	/* Initialize MIPI DSI */
 	ret = kmb_dsi_init(drm, adv_bridge);
-	if (ret == -EPROBE_DEFER) {
-		DRM_INFO("%s: wait for external bridge driver DT", __func__);
-		return -EPROBE_DEFER;
-	} else if (ret) {
+	if (ret) {
 		DRM_ERROR("failed to initialize DSI\n");
 		goto setup_fail;
 	}
diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h
index 9e3bb83..596f4fe 100644
--- a/drivers/gpu/drm/kmb/kmb_drv.h
+++ b/drivers/gpu/drm/kmb/kmb_drv.h
@@ -108,6 +108,20 @@  static inline void kmb_write_msscam(struct kmb_drm_private *dev_p,
 	writel(value, (dev_p->msscam_mmio + reg));
 }
 
+static inline u32 kmb_read_msscam(struct kmb_drm_private *dev_p,
+		unsigned int reg)
+{
+	return readl(dev_p->msscam_mmio + reg);
+}
+
+static inline void kmb_set_bitmask_msscam(struct kmb_drm_private *dev_p,
+		unsigned int reg, u32 mask)
+{
+	u32 reg_val = kmb_read_msscam(dev_p, reg);
+
+	kmb_write_msscam(dev_p, reg, (reg_val | mask));
+}
+
 static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg)
 {
 	return readl(dev_p->lcd_mmio + reg);
diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c
index af04eb9..8ab4de7 100644
--- a/drivers/gpu/drm/kmb/kmb_dsi.c
+++ b/drivers/gpu/drm/kmb/kmb_dsi.c
@@ -814,9 +814,11 @@  static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p,
 		active_vchannels++;
 
 		/*connect lcd to mipi */
-		kmb_write_msscam(dev_p, MSS_CAM_BASE_ADDR +
-				MIPI_TX_MSS_LCD_MIPI_CFG, 1);
+		kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1);
 
+		/*stop iterating as only one virtual channel shall be used for
+		 * LCD connection
+		 */
 		break;
 	}
 
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h
index f8a7abf..20b331d 100644
--- a/drivers/gpu/drm/kmb/kmb_regs.h
+++ b/drivers/gpu/drm/kmb/kmb_regs.h
@@ -697,6 +697,11 @@ 
 			& (1 << (dphy - MIPI_DPHY6)))
 #define DPHY_CFG_CLK_EN				(0x18c)
 
-#define MIPI_TX_MSS_LCD_MIPI_CFG		(0x04)
+#define MSS_LCD_MIPI_CFG		(0x04)
+#define MSS_CAM_CLK_CTRL		(0x10)
+#define   LCD				(1<<1)
+#define   MIPI_COMMON			(1<<2)
+#define   MIPI_TX0			(1<<9)
+
 #define BIT_MASK_16				(0xffff)
 #endif /* __KMB_REGS_H__ */