diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a8a3ffcef5dc..0a535932ed18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5404,26 +5404,37 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 	enum pipe pipe = crtc->pipe;
 	u32 pattern_val, dp_tp_ctl;
+	i915_reg_t dp_tp_reg, dp_comp_reg;
+
+	if (IS_ELKHARTLAKE(dev_priv))
+		dp_tp_reg = DP_TP_CTL(dig_port->base.port);
+	else if (IS_TIGERLAKE(dev_priv))
+		dp_tp_reg = TGL_DP_TP_CTL(pipe);
+
+	if (IS_ELKHARTLAKE(dev_priv))
+		dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port);
+	else if (IS_TIGERLAKE(dev_priv))
+		dp_comp_reg = DDI_DP_COMP_CTL(pipe);
 
 	switch (data->phy_pattern) {
 	case DP_PHY_TEST_PATTERN_NONE:
 		DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
-		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+		intel_de_write(dev_priv, dp_comp_reg, 0x0);
 		break;
 	case DP_PHY_TEST_PATTERN_D10_2:
 		DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
-		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+		intel_de_write(dev_priv, dp_comp_reg,
 			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
 		break;
 	case DP_PHY_TEST_PATTERN_ERROR_COUNT:
 		DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
-		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+		intel_de_write(dev_priv, dp_comp_reg,
 			       DDI_DP_COMP_CTL_ENABLE |
 			       DDI_DP_COMP_CTL_SCRAMBLED_0);
 		break;
 	case DP_PHY_TEST_PATTERN_PRBS7:
 		DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
-		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+		intel_de_write(dev_priv, dp_comp_reg,
 			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
 		break;
 	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
@@ -5432,14 +5443,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 		 * current firmware of DPR-100 could not set it, so hardcoding
 		 * now for complaince test.
 		 */
-		DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
+		DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \
+			      0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
 		pattern_val = 0x3e0f83e0;
-		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+		if (IS_ELKHARTLAKE(dev_priv))
+			intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0),
+				       pattern_val);
+		else
+			intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
 		pattern_val = 0x0f83e0f8;
-		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+		if (IS_ELKHARTLAKE(dev_priv))
+			intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1),
+				       pattern_val);
+		else
+			intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
 		pattern_val = 0x0000f83e;
-		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
-		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+		if (IS_ELKHARTLAKE(dev_priv))
+			intel_de_write(dev_priv, EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2),
+				       pattern_val);
+		else
+			intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
+		intel_de_write(dev_priv, dp_comp_reg,
 			       DDI_DP_COMP_CTL_ENABLE |
 			       DDI_DP_COMP_CTL_CUSTOM80);
 		break;
@@ -5451,20 +5475,20 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 		 */
 		DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
 		pattern_val = 0xFB;
-		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+		intel_de_write(dev_priv, dp_comp_reg,
 			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
 			       pattern_val);
 		break;
-		case DP_PHY_TEST_PATTERN_CP2520_PAT3:
-			DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
-			intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
-			dp_tp_ctl = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
-			dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
-			dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a;
-			dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
-			dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
-			intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl);
-			break;
+	case DP_PHY_TEST_PATTERN_CP2520_PAT3:
+		DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
+		intel_de_write(dev_priv, dp_comp_reg, 0x0);
+		dp_tp_ctl = intel_de_read(dev_priv, dp_tp_reg);
+		dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
+		dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a;
+		dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
+		dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
+		intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl);
+		break;
 	default:
 		WARN(1, "Invalid Phy Test Pattern\n");
 	}
@@ -5478,22 +5502,32 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
+	u32 trans_ddi_func_ctl_value, trans_conf_value,
+		dp_tp_ctl_value, trans_ddi_port_mask;
+	i915_reg_t dp_tp_reg;
+
+	if (IS_ELKHARTLAKE(dev_priv)) {
+		dp_tp_reg = DP_TP_CTL(dig_port->base.port);
+		trans_ddi_port_mask = TRANS_DDI_PORT_MASK;
+	} else if (IS_TIGERLAKE(dev_priv)) {
+		dp_tp_reg = TGL_DP_TP_CTL(pipe);
+		trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK;
+	}
 
 	trans_ddi_func_ctl_value = intel_de_read(dev_priv,
 						 TRANS_DDI_FUNC_CTL(pipe));
 	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
-	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
 
+	dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg);
 	trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
-				      TGL_TRANS_DDI_PORT_MASK);
+				      trans_ddi_port_mask);
 	trans_conf_value &= ~PIPECONF_ENABLE;
 	dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
 
 	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
 	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
 		       trans_ddi_func_ctl_value);
-	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
+	intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value);
 }
 
 static void
@@ -5505,20 +5539,29 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
 	enum port port = dig_port->base.port;
 	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
+	u32 trans_ddi_func_ctl_value, trans_conf_value,
+		dp_tp_ctl_value, trans_ddi_sel_port;
+	i915_reg_t dp_tp_reg;
+
+	if (IS_ELKHARTLAKE(dev_priv)) {
+		dp_tp_reg = DP_TP_CTL(port);
+		trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port);
+	} else if (IS_TIGERLAKE(dev_priv)) {
+		dp_tp_reg = TGL_DP_TP_CTL(pipe);
+		trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port);
+	}
 
 	trans_ddi_func_ctl_value = intel_de_read(dev_priv,
 						 TRANS_DDI_FUNC_CTL(pipe));
 	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
-	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
-
+	dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg);
 	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
-				    TGL_TRANS_DDI_SELECT_PORT(port);
+				    trans_ddi_sel_port;
 	trans_conf_value |= PIPECONF_ENABLE;
 	dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
 
 	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
-	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
+	intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value);
 	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
 		       trans_ddi_func_ctl_value);
 }
@@ -5590,6 +5633,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
 		response = intel_dp_autotest_edid(intel_dp);
 		break;
 	case DP_TEST_LINK_PHY_TEST_PATTERN:
+		if (!IS_ELKHARTLAKE(dev_priv) && !IS_TIGERLAKE(dev_priv)) {
+			DRM_DEBUG_KMS( \
+				"PHY compliance for platform not supported\n");
+			return;
+		}
 		drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
 		response = intel_dp_autotest_phy_pattern(intel_dp);
 		break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4850890918dc..7d3b6779661f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10026,10 +10026,16 @@ enum skl_power_gate {
 #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
 #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
 
+/* EHL/JSL DP compliance control */
+#define _EHL_DDI_DP_COMP_CTL_A		0x640F0
+#define _EHL_DDI_DP_COMP_CTL_B		0x641F0
+#define EHL_DDI_DP_COMP_CTL(port) \
+	_MMIO_PORT(port, _EHL_DDI_DP_COMP_CTL_A, _EHL_DDI_DP_COMP_CTL_B)
+
 /* DDI DP Compliance Control */
-#define _DDI_DP_COMP_CTL_A			0x605F0
-#define _DDI_DP_COMP_CTL_B			0x615F0
-#define DDI_DP_COMP_CTL(pipe)			_MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
+#define _DDI_DP_COMP_CTL_A		0x605F0
+#define _DDI_DP_COMP_CTL_B		0x615F0
+#define DDI_DP_COMP_CTL(pipe)		_MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
 #define   DDI_DP_COMP_CTL_ENABLE		(1 << 31)
 #define   DDI_DP_COMP_CTL_D10_2			(0 << 28)
 #define   DDI_DP_COMP_CTL_SCRAMBLED_0		(1 << 28)
@@ -10039,6 +10045,12 @@ enum skl_power_gate {
 #define   DDI_DP_COMP_CTL_SCRAMBLED_1		(5 << 28)
 #define   DDI_DP_COMP_CTL_HBR2_RESET		(0xFC << 0)
 
+/* EHL */
+#define _EHL_DDI_DP_COMP_PAT_A	0x640F4
+#define _EHL_DDI_DP_COMP_PAT_B	0x641F4
+#define EHL_DDI_DP_COMP_PAT(port, i) \
+	_MMIO(_PORT(port, _EHL_DDI_DP_COMP_PAT_A, _EHL_DDI_DP_COMP_PAT_B) + (i) * 4)
+
 /* DDI DP Compliance Pattern */
 #define _DDI_DP_COMP_PAT_A			0x605F4
 #define _DDI_DP_COMP_PAT_B			0x615F4
