From patchwork Thu May 23 12:59:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B0D6C25B75 for ; Thu, 23 May 2024 12:59:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C780A10E4E2; Thu, 23 May 2024 12:59:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="dOc3RQbH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA23910E4E2 for ; Thu, 23 May 2024 12:59:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716469192; x=1748005192; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rs3z9HzdRBzbBCkQW5guuWz+ROPpqO5uAFFVkKdV55c=; b=dOc3RQbHtuPFo8TxFcFfAPVGpxvC9G1XQkfyNvX8JO2XISh6wDei6z9o F3rfdBnQpKSDckCC78Y+A/3JYibWKKF2s3F5D/CuVO13AQbwuOOp8/pA5 RpjZEy7X1cJZIHEo/X02r0UKEvIdG9SHbwqqVfUiJFzyKpahApP9Hhn0d PfjHgbR0+DXbKq23PTy1SLIR/UerdIPZM9a6MO80dLWmCSHdtG1bbF7aw QQ88j9kiDUZfSIOPQza+BmhqMcBdY6uUXg7CAmO5+e+fp/RNmdGhC8KNK lqVm9tl7JSf+UJTFA47kS1ke4cuOgxUMQNVftcCvwBo0VU++ZMfZxfHpZ A==; X-CSE-ConnectionGUID: ixOwJBnwS0iz/VJYbgMRww== X-CSE-MsgGUID: tllykwjZTQmBaYzq1N5xjQ== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="38164655" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="38164655" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 05:59:52 -0700 X-CSE-ConnectionGUID: wO8v6RT4RQORPTmn9Zxx/w== X-CSE-MsgGUID: iMP9njP2ROuW2jHlVzab6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33731553" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 05:59:51 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 01/16] drm/i915: pass dev_priv explicitly to DSPADDR_VLV Date: Thu, 23 May 2024 15:59:29 +0300 Message-Id: <1d9be6b1eedd9240468a89cd3a10e8513caa33b1.1716469091.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPADDR_VLV register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 1f05f9184cb2..4636523d7948 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -577,7 +577,7 @@ vlv_primary_async_flip(struct intel_plane *plane, u32 dspaddr_offset = plane_state->view.color_plane[0].offset; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane), + intel_de_write_fw(dev_priv, DSPADDR_VLV(dev_priv, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index d74a74d1f29a..926da106f1a2 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -9,7 +9,7 @@ #include "intel_display_reg_defs.h" #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) +#define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) #define _DSPACNTR 0x70180 #define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)