From patchwork Fri Apr 26 13:01:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13644768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BBB6C4345F for ; Fri, 26 Apr 2024 13:04:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C3A4011239D; Fri, 26 Apr 2024 13:04:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CEFjITV1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6276911239D; Fri, 26 Apr 2024 13:04:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714136648; x=1745672648; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CBzWM4z2gF5FXhFR/phE7JsraCYg9Dizz6dSpHQob0Q=; b=CEFjITV1Q8YwKZF+dkSu/leYuJK9Q9q/JwvbwY5onkTjNJB9euifuhwk pn74UCC5fmDIWYHq2C6tUbkUvSr/B/zJKCcv7mUuO0BXLAjsqs60T68G1 texIJqD+ASJfxk/LGct6j9aSpxECNZu3VoxXjjJw4mXewSRwzSjiJt5nK GQ07tvsTYyoooO+GDGrDkCFTkkPY+Bet+ctrFZgkuNSampmdZ/QeF+n1t 7S+8ARyR3EZaQ7KfEHtT1KQV6m+pKmrdpBxDElip2c2ZnT1USKfdK7Ig2 XVOhiseCNevTV6H1rwWGeFGcOdhJEOGoC8tyWaXXtQeFv5BzpHNbPNWh0 g==; X-CSE-ConnectionGUID: YGF8QnyHQH+dswI9HzF84w== X-CSE-MsgGUID: a0k6eaj4S5m2DX/GSFmSKQ== X-IronPort-AV: E=McAfee;i="6600,9927,11056"; a="12804116" X-IronPort-AV: E=Sophos;i="6.07,232,1708416000"; d="scan'208";a="12804116" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 06:04:07 -0700 X-CSE-ConnectionGUID: OCDE+NEaSseiUKL3v9rKqg== X-CSE-MsgGUID: uWYQF0QeS/SqG0b/XnsutQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,232,1708416000"; d="scan'208";a="25405524" Received: from dgarbuz-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.48.145]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 06:04:06 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 007/123] drm/i915: pass dev_priv explicitly to PIPE_CRC_RES_3_IVB Date: Fri, 26 Apr 2024 16:01:32 +0300 Message-Id: <1dbb2c9a72239a97a0479cfcb73adde9939aaa73.1714136165.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_3_IVB register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index d810a0bab901..a17c258bb219 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -366,7 +366,7 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, display_pipe_crc_irq_handler(dev_priv, pipe, intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)), intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)), intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7b7b9f73db02..248312e6e06e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1652,7 +1652,7 @@ #define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) #define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) #define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) -#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) +#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB)