| Message ID | 20090929030123.GB32077@zhen-devel.sh.intel.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
On Tue, 29 Sep 2009 11:01:23 +0800 Zhenyu Wang <zhenyuw@linux.intel.com> wrote: > On 2009.09.28 10:38:14 -0700, Jesse Barnes wrote: > > On Fri, 25 Sep 2009 16:01:29 +0800 > > Zhenyu Wang <zhenyuw@linux.intel.com> wrote: > > > > > Until we figure out the right setting for powersave features on > > > Ironlake, disable it for now, also disable watermark update, > > > which has new registers for it on Ironlake too. > > > > > > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_dma.c | 3 +++ > > > drivers/gpu/drm/i915/intel_display.c | 3 +++ > > > 2 files changed, 6 insertions(+), 0 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_dma.c > > > b/drivers/gpu/drm/i915/i915_dma.c index 45d507e..733f051 100644 > > > --- a/drivers/gpu/drm/i915/i915_dma.c > > > +++ b/drivers/gpu/drm/i915/i915_dma.c > > > @@ -1202,6 +1202,9 @@ static int i915_load_modeset_init(struct > > > drm_device *dev, if (IS_I965G(dev) || IS_G33(dev)) > > > dev_priv->cursor_needs_physical = false; > > > > > > + if (IS_IGDNG(dev)) > > > + i915_powersave = 0; > > > > Can you use the new function pointer code instead? Just make no-ops > > for the watermark update functions and the other stuff that doesn't > > work... > > > > yeah, that'll be better. How about this one? > > From 26f1a7aad7c990b3d6c600bd03eb41fbc2274d68 Mon Sep 17 00:00:00 2001 > From: Zhenyu Wang <zhenyuw@linux.intel.com> > Date: Tue, 29 Sep 2009 03:54:53 +0800 > Subject: [PATCH] drm/i915: disable powersave feature for Ironlake > currently > > Until we figure out the right setting for powersave features on > Ironlake, disable it for now. Also disable watermark update, > which has new registers for it on Ironlake too. > > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Yeah, that looks better. Thanks. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Jesse
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 45d507e..4af7c7c 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1227,8 +1227,7 @@ static int i915_load_modeset_init(struct drm_device *dev, goto out; /* Try to set up FBC with a reasonable compressed buffer size */ - if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev) || IS_GM45(dev)) && - i915_powersave) { + if (I915_HAS_FBC(dev) && i915_powersave) { int cfb_size; /* Try to get an 8M buffer... */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b24b2d1..d378a1a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -979,7 +979,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) -#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev))) +#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev) || IS_GM45(dev)) \ + && !IS_IGDNG(dev)) #define PRIMARY_RINGBUFFER_SIZE (128*1024) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 10c42e5..a134b4a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2587,6 +2587,9 @@ static void intel_update_watermarks(struct drm_device *dev) unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; int enabled = 0, pixel_size = 0; + if (!dev_priv->display.update_wm) + return; + /* Get the clock config from both planes */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { intel_crtc = to_intel_crtc(crtc); @@ -4140,7 +4143,9 @@ void intel_init_clock_gating(struct drm_device *dev) * Disable clock gating reported to work incorrectly according to the * specs, but enable as much else as we can. */ - if (IS_G4X(dev)) { + if (IS_IGDNG(dev)) { + return; + } else if (IS_G4X(dev)) { uint32_t dspclk_gate; I915_WRITE(RENCLK_GATE_D1, 0); I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | @@ -4228,7 +4233,9 @@ static void intel_init_display(struct drm_device *dev) i830_get_display_clock_speed; /* For FIFO watermark updates */ - if (IS_G4X(dev)) + if (IS_IGDNG(dev)) + dev_priv->display.update_wm = NULL; + else if (IS_G4X(dev)) dev_priv->display.update_wm = g4x_update_wm; else if (IS_I965G(dev)) dev_priv->display.update_wm = i965_update_wm;