b/drivers/gpu/drm/i915/i915_drv.h index 6035d3d..416c01e 100644
@@ -187,6 +187,7 @@ typedef struct drm_i915_private {
unsigned int status_gfx_addr;
drm_local_map_t hws_map;
struct drm_gem_object *hws_obj;
+ struct drm_gem_object *pwrctx;
struct resource mch_res;
@@ -280,6 +281,7 @@ typedef struct drm_i915_private {
u32 saveDSPBCNTR;
u32 saveDSPARB;
u32 saveRENDERSTANDBY;
+ u32 savePWRCTXA;
u32 saveHWS;
u32 savePIPEACONF;
u32 savePIPEBCONF;
@@ -982,6 +984,7 @@ extern int i915_wait_ring(struct drm_device * dev,
int n, const char *caller); #define HAS_FW_BLC(dev)
(IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) #define
HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) #define
I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) ||
IS_I965G(dev))) +#define I915_HAS_RC6(dev) (IS_I965GM(dev) ||
IS_GM45(dev) || IS_IGDNG_M(dev)) #define
PRIMARY_RINGBUFFER_SIZE (128*1024)
b/drivers/gpu/drm/i915/i915_reg.h index 0466ddb..3a2e090 100644
@@ -260,6 +260,8 @@
#define HWS_PGA 0x02080
#define HWS_ADDRESS_MASK 0xfffff000
#define HWS_START_ADDRESS_SHIFT 4
+#define PWRCTXA 0x2088 /* 965GM+ only */
+#define PWRCTX_EN (1<<0)
#define IPEIR 0x02088
#define IPEHR 0x0208c
#define INSTDONE 0x02090
@@ -769,7 +771,8 @@
/** GM965 GM45 render standby register */
#define MCHBAR_RENDER_STANDBY 0x111B8
-
+#define RCX_SW_EXIT (1<<23)
+#define RSX_STATUS_MASK 0x00700000
#define PEG_BAND_GAP_DATA 0x14d68
/*