From patchwork Tue Feb 2 18:30:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Garrett X-Patchwork-Id: 76434 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o12IUs6a006307 for ; Tue, 2 Feb 2010 18:31:30 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E55109EE3B; Tue, 2 Feb 2010 10:30:53 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from cavan.codon.org.uk (cavan.codon.org.uk [93.93.128.6]) by gabe.freedesktop.org (Postfix) with ESMTP id C85709E839 for ; Tue, 2 Feb 2010 10:30:51 -0800 (PST) Received: from mjg59 by cavan.codon.org.uk with local (Exim 4.69) (envelope-from ) id 1NcNWR-0000hl-Uf; Tue, 02 Feb 2010 18:30:47 +0000 Date: Tue, 2 Feb 2010 18:30:47 +0000 From: Matthew Garrett To: Jesse Barnes Message-ID: <20100202183047.GA2042@srcf.ucam.org> References: <20100127121037.78f0cfc2@jbarnes-piketon> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20100127121037.78f0cfc2@jbarnes-piketon> User-Agent: Mutt/1.5.18 (2008-05-17) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: mjg59@cavan.codon.org.uk X-SA-Exim-Scanned: No (on cavan.codon.org.uk); SAEximRunCond expanded to false Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] drm/i915: add dynamic performance control support for Ironlake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 02 Feb 2010 18:31:30 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 301d77c..8532aea 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -452,7 +452,7 @@ typedef struct drm_i915_private { u32 savePIPEB_DATA_N1; u32 savePIPEB_LINK_M1; u32 savePIPEB_LINK_N1; - u32 saveRSTDBYCTL; + u32 saveMCHBAR_RENDER_STANDBY; struct { struct drm_mm gtt_space; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 18370ac..3559afa 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -272,23 +272,23 @@ static void i915_hotplug_work_func(struct work_struct *work) static void i915_handle_rps_change(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; - u32 slow_up, slow_down, max_avg, min_avg; + u32 busy_up, busy_down, max_avg, min_avg; u16 rgvswctl; u8 new_delay = dev_priv->cur_delay; I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG); - slow_up = I915_READ(RCPREVBSYTUPAVG); - slow_down = I915_READ(RCPREVBSYTDNAVG); + busy_up = I915_READ(RCPREVBSYTUPAVG); + busy_down = I915_READ(RCPREVBSYTDNAVG); max_avg = I915_READ(RCBMAXAVG); min_avg = I915_READ(RCBMINAVG); /* Handle RCS change request from hw */ - if (slow_up > max_avg) { + if (busy_up > max_avg) { if (dev_priv->cur_delay != dev_priv->max_delay) new_delay = dev_priv->cur_delay - 1; if (new_delay < dev_priv->max_delay) new_delay = dev_priv->max_delay; - } else if (slow_down < min_avg) { + } else if (busy_down < min_avg) { if (dev_priv->cur_delay != dev_priv->min_delay) new_delay = dev_priv->cur_delay + 1; if (new_delay > dev_priv->min_delay) @@ -300,8 +300,8 @@ static void i915_handle_rps_change(struct drm_device *dev) rgvswctl = I915_READ(MEMSWCTL); if (rgvswctl & MEMCTL_CMD_STS) { - DRM_ERROR("gpu slow, RCS change rejected\n"); - return; /* still slow with another command */ + DRM_ERROR("gpu busy, RCS change rejected\n"); + return; /* still busy with another command */ } /* Program the new state */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 487b818..30cc9c9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -903,7 +903,7 @@ #define RCBMINAVG 0x111a0 #define RCUPEI 0x111b0 #define RCDNEI 0x111b4 -#define RSTDBYCTL 0x111b8 +#define MCHBAR_RENDER_STANDBY 0x111b8 #define RCX_SW_EXIT (1<<23) #define RSX_STATUS_MASK 0x00700000 #define VIDCTL 0x111c0 diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 2c34664..ac0d1a7 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -682,7 +682,8 @@ void i915_restore_display(struct drm_device *dev) I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL); - I915_WRITE(RSTDBYCTL, dev_priv->saveRSTDBYCTL); + I915_WRITE(MCHBAR_RENDER_STANDBY, + dev_priv->saveMCHBAR_RENDER_STANDBY); } else { I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); @@ -746,7 +747,8 @@ int i915_save_state(struct drm_device *dev) dev_priv->saveGTIMR = I915_READ(GTIMR); dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR); dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR); - dev_priv->saveRSTDBYCTL = I915_READ(RSTDBYCTL); + dev_priv->saveMCHBAR_RENDER_STANDBY = + I915_READ(MCHBAR_RENDER_STANDBY); } else { dev_priv->saveIER = I915_READ(IER); dev_priv->saveIMR = I915_READ(IMR); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fd36dfe..d014132 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4591,8 +4591,8 @@ void intel_init_clock_gating(struct drm_device *dev) if (obj_priv) { I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); - I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & - ~RCX_SW_EXIT); + I915_WRITE(MCHBAR_RENDER_STANDBY, + I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); } } }