From patchwork Thu Jun 17 20:32:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 106738 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o5HKY4ZG002073 for ; Thu, 17 Jun 2010 20:34:40 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FA519E921 for ; Thu, 17 Jun 2010 13:34:04 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from cpoproxy3-pub.bluehost.com (cpoproxy3-pub.bluehost.com [67.222.54.6]) by gabe.freedesktop.org (Postfix) with SMTP id B80AB9E73F for ; Thu, 17 Jun 2010 13:33:52 -0700 (PDT) Received: (qmail 29640 invoked by uid 0); 17 Jun 2010 20:33:52 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by cpoproxy3.bluehost.com with SMTP; 17 Jun 2010 20:33:52 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=virtuousgeek.org; h=Received:Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References:X-Mailer:Mime-Version:Content-Type:X-Identified-User; b=lKDoecznMV+mdich/n11ZcX5kItZDvcgAZLGjaSHdBd+vMkMDD61fKc5eLBiB7YQrmdORfoM1nW3MVP5d698o5GJou3TeAFwn3YKkeq+ndDFRJ48GVI9QqcjR0CwsWqm; Received: from [75.110.194.140] (helo=localhost) by box514.bluehost.com with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.69) (envelope-from ) id 1OPLmZ-0003Ze-Vr; Thu, 17 Jun 2010 14:33:52 -0600 Date: Thu, 17 Jun 2010 13:32:17 -0700 From: Jesse Barnes To: Andrew Lutomirski Message-ID: <20100617133217.5babef34@virtuousgeek.org> In-Reply-To: References: <87typ5qgbp.fsf@yoom.home.cworth.org> <201006151605.15891.damnshock@gmail.com> <89khjo$fmu93d@orsmga002.jf.intel.com> <201006161325.49626.damnshock@gmail.com> X-Mailer: Claws Mail 3.7.5 (GTK+ 2.18.9; x86_64-redhat-linux-gnu) Mime-Version: 1.0 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 75.110.194.140 authed with jbarnes@virtuousgeek.org} Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [ANNOUNCE] xf86-video-intel 2.11.901 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 17 Jun 2010 20:34:40 +0000 (UTC) From a8ddc8b3743abb72b6c7e26ce75ae98d93d92133 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Mon, 5 Apr 2010 14:03:51 -0700 Subject: [PATCH 3/3] drm/i915: don't queue flips during a flip pending event Hardware will set the flip pending ISR bit as soon as it receives the flip instruction, and (supposedly) clear it once the flip completes (e.g. at the next vblank). If we try to send down a flip instruction while the ISR bit is set, the hardware can become very confused, and we may never receive the corresponding flip pending interrupt, effectively hanging the chip. Fixes fdo bug #27040. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6f5e7f5..24853e1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4235,6 +4235,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, unsigned long flags; int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC; int ret, pipesrc; + u32 flip_mask; RING_LOCALS; work = kzalloc(sizeof *work, GFP_KERNEL); @@ -4285,6 +4286,15 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, atomic_inc(&obj_priv->pending_flip); work->pending_flip_obj = obj; + if (intel_crtc->plane) + flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; + else + flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT; + + /* Wait for any previous flip to finish */ + while (I915_READ(ISR) & flip_mask) + ; + BEGIN_LP_RING(4); if (IS_I965G(dev)) { OUT_RING(MI_DISPLAY_FLIP | -- 1.6.6.1