From patchwork Fri Mar 7 20:40:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 3794721 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3DE84BF540 for ; Fri, 7 Mar 2014 20:40:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 21ACA202F2 for ; Fri, 7 Mar 2014 20:40:30 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2C48B20304 for ; Fri, 7 Mar 2014 20:40:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C3C88FADAA; Fri, 7 Mar 2014 12:40:26 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ig0-f171.google.com (mail-ig0-f171.google.com [209.85.213.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 016D1FADAA for ; Fri, 7 Mar 2014 12:40:25 -0800 (PST) Received: by mail-ig0-f171.google.com with SMTP id hl1so2962342igb.4 for ; Fri, 07 Mar 2014 12:40:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=LSDx7dqeECAH5RcoUxXjAfuKvXSsqh+b35BWmwslaSI=; b=ThnKaNnrgitEO/PdAddIXYMQlOjw4tPGFzjHBoTp7UnWUHt7XAYYGSjVqiQTWIjs+E hCRU4qKN6X8NwON4ux1g8oQ/RZQQELuaoHGVDgAnGebzMiR8xNDqNBl+G5p6zBpJMHxK JFqnvCRtvtu6S/7EUiRp+4KRiLD8EzS0AR0TnMMcO33r+uxAI3tDBk/1nNsqRp9hduHe cjGc1DIT+qQ75yIVYnlPMSCdlZees6tLKpWOYu0Mh8ogHJCjmQqpWHpSuaobRZJSZeFN zykfr4VmguSdgEoTcn44IGUUMyiTEmbwCkTkjYFSN0axTR4IcrZwULiq2HL6swFtN/cL iZqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-type:content-disposition:in-reply-to :user-agent; bh=LSDx7dqeECAH5RcoUxXjAfuKvXSsqh+b35BWmwslaSI=; b=SSQx7btSJ74wZfqsZU5InC3/R2lNY2DChjGK+6LCO507yDsNQQ2Zs7Tq6v+Z8qDaJt XgzA+/8g/9i874a4y4yrLdEVFxZl9l7H/9/C5sPntoevZ4WjDxDY10GmoQ8MGfQF8juw bQJRn89WEmVZmyTuqJiZiuh/MypYexHyVlsglS7Hcs76NKfLT+bgIf5tVarsv0OkFKh4 csi6azHc0+cej8vIx2bLb6riygXLvMNVNUwysGFN8P8JmY1NkNRlYnICPDbHWpuQMhFF M3n00Jh0z8KPAkfrQhLblezWwF6VnXOcWIQz+6wirfmuTd0YFy45xVCkzeEfbYXMlVdw sOvw== X-Gm-Message-State: ALoCoQnaqdUkSR6PMKNah98g3we4hzWjJMQLIvevyaNlPU2e04WZcsDcQpQnz7iLzuXQJfDsnsrYCr5rUHECOhBJ4wHFyl517PgXP0uf5lEedSTJCvK8GfjsGyzUkFnY5eefWb4qUYM9qmBmrYQuDOsz3ImbhJi6q8xKYsz5mRNfx39Kyw5aa82DXwlPyJQYJwHu6dH/Ua6LEmla6P/TTjRPEY8NBt7zpg== X-Received: by 10.42.50.3 with SMTP id y3mr16974688icf.12.1394224825526; Fri, 07 Mar 2014 12:40:25 -0800 (PST) Received: from google.com ([172.16.49.23]) by mx.google.com with ESMTPSA id rj10sm5909912igc.8.2014.03.07.12.40.23 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 07 Mar 2014 12:40:24 -0800 (PST) Date: Fri, 7 Mar 2014 13:40:21 -0700 From: Bjorn Helgaas To: Paul Bolle Message-ID: <20140307204021.GA9822@google.com> References: <1391886379.2669.11.camel@x41> <1391890927.1882.5.camel@x41> <1391951759.6036.7.camel@artifact> <1391952344.25424.4.camel@x220> <1394185698.5608.5.camel@x41> <1394212609.1987.6.camel@x41> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1394212609.1987.6.camel@x41> User-Agent: Mutt/1.5.21 (2010-09-15) Cc: David Airlie , Daniel Vetter , intel-gfx , Linux Kernel Mailing List , Yinghai Lu Subject: Re: [Intel-gfx] agp/intel: can't ioremap flush page - no chipset flushing X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,RCVD_IN_DNSWL_MED,T_DKIM_INVALID,T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Fri, Mar 07, 2014 at 06:16:49PM +0100, Paul Bolle wrote: > Bjorn Helgaas schreef op vr 07-03-2014 om 09:55 [-0700]: > > On Fri, Mar 7, 2014 at 2:48 AM, Paul Bolle wrote: > > > This might end up not being relevant. And this is surely documented > > > somewhere, but anyhow: > > > - what git magic returns the hashes of the 15 commits that merge commit > > > 96702be56037 added to the tree; and > > > > "git show 96702be56037" gives: > > > > commit 96702be560374ee7e7139a34cab03554129abbb4 > > Merge: 04f982beb900 d56dbf5bab8c > > ... > > > > 04f982beb900 is the previous HEAD, d56dbf5bab8c is the head of the > > branch merged by this commit. "git log 04f982beb900..96702be56037" > > shows the commits merged. > > Thanks. Fairly obvious, actually. Not sure why I didn't think of this > myself. > > > > - how can I use the list of those hashes to limit the range of commits > > > to do a git bisect? > > > > I'm not a git bisect expert, but I *think* you should be able to do > > something like this: > > > > git bisect start > > git bisect bad 96702be56037 > > git bisect good 04f982beb900 > > > > (assuming you've verified that 96702be56037 really *is* bad and > > 04f982beb900 really *is* good), and git should checkout something in > > the middle and you can build and test it, then use "git bisect good" > > or "git bisect bad" depending on the result. > > Makes sense. Thanks again. 04f982beb900 appears to be good. So if > 96702be56037 turns out to be bad bisecting might not turn into the > ordeal it usually is. (On this machine, with my workflow, bisecting an > v3.x..v3.x+1-rcy range takes a few days.) It seems quite possible that I broke pci_bus_alloc_resource(), which could cause an allocation failure like this. If you have a chance to try it, here's a debug patch against v3.14-rc5. It should apply cleanly to 96702be56037. If you can try it, please attach the dmesg log to the bugzilla. Bjorn diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 5c85350f4c3d..0dbba6c7c001 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -997,6 +997,7 @@ static int intel_alloc_chipset_flush_resource(void) ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, PAGE_SIZE, PCIBIOS_MIN_MEM, 0, pcibios_align_resource, intel_private.bridge_dev); + dev_info(&intel_private.bridge_dev->dev, "pci_bus_alloc ret %d\n", ret); return ret; } @@ -1007,6 +1008,7 @@ static void intel_i915_setup_chipset_flush(void) u32 temp; pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); + dev_info(&intel_private.bridge_dev->dev, "I915_IFPADDR %#010x\n", temp); if (!(temp & 0x1)) { intel_alloc_chipset_flush_resource(); intel_private.resource_valid = 1; @@ -1022,6 +1024,7 @@ static void intel_i915_setup_chipset_flush(void) if (ret) intel_private.resource_valid = 0; } + dev_info(&intel_private.bridge_dev->dev, "ifp_resource %pR\n", &intel_private.ifp_resource); } static void intel_i965_g33_setup_chipset_flush(void) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index 00660cc502c5..1c6d75ae34d9 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -146,24 +146,31 @@ static int pci_bus_alloc_from_region(struct pci_bus *bus, struct resource *res, type_mask |= IORESOURCE_IO | IORESOURCE_MEM; + dev_info(&bus->dev, "%s: alloc %pR size %#llx from bus region [%#010llx-%#010llx]\n", __func__, res, (long long) size, (long long) region->start, (long long) region->end); pci_bus_for_each_resource(bus, r, i) { if (!r) continue; /* type_mask must match */ - if ((res->flags ^ r->flags) & type_mask) + if ((res->flags ^ r->flags) & type_mask) { + dev_info(&bus->dev, "%s: %pR: wrong type (%#lx %#lx mask %#x)\n", __func__, r, res->flags, r->flags, type_mask); continue; + } /* We cannot allocate a non-prefetching resource from a pre-fetching area */ if ((r->flags & IORESOURCE_PREFETCH) && - !(res->flags & IORESOURCE_PREFETCH)) + !(res->flags & IORESOURCE_PREFETCH)) { + dev_info(&bus->dev, "%s: %pR: wrong prefetchability\n", __func__, r); continue; + } avail = *r; pci_clip_resource_to_region(bus, &avail, region); - if (!resource_size(&avail)) + if (!resource_size(&avail)) { + dev_info(&bus->dev, "%s: %pR: no space (avail %pR)\n", __func__, r, &avail); continue; + } /* * "min" is typically PCIBIOS_MIN_IO or PCIBIOS_MIN_MEM to @@ -179,6 +186,7 @@ static int pci_bus_alloc_from_region(struct pci_bus *bus, struct resource *res, /* Ok, try it out.. */ ret = allocate_resource(r, res, size, min, max, align, alignf, alignf_data); + dev_info(&bus->dev, "%s: %pR: alloc from %#llx-%#llx, ret %d\n", __func__, r, min, max, ret); if (ret == 0) return 0; }