From patchwork Mon Aug 15 14:41:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Bragg X-Patchwork-Id: 9281147 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B793D607FD for ; Mon, 15 Aug 2016 14:41:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A8D9728CF7 for ; Mon, 15 Aug 2016 14:41:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9DB0528D0B; Mon, 15 Aug 2016 14:41:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4F75428CF7 for ; Mon, 15 Aug 2016 14:41:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 83FF66E55C; Mon, 15 Aug 2016 14:41:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id A5CCC6E558; Mon, 15 Aug 2016 14:41:40 +0000 (UTC) Received: by mail-wm0-x244.google.com with SMTP id i5so11477717wmg.2; Mon, 15 Aug 2016 07:41:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=M6ruaLGEiw5B6IksG1Q4Y4RLvYCCrNywxBXb/mioalo=; b=ryr+WHF0aUigPS12hurOuShQBBKDnn5gNUQh9oOSeQSN6H04s8ga/DuTIb0u5ZHxVL BBCgVOM/4WnreSTT+VfAi6YgDSmXwgTOEIq2yakvhMPziroch4ngY6Oem0UUnI2+D7i7 3PIWUKa+fTc5UyLsKm//iSg2IriyrehfpvzbuFCuPN3y1xJYpPcGyl5QDJyZOhw/ICuG I4A9YXyKBBzWGl3k2iqGQd1aWTOqDO4qSyJdaxHc36/zHFwAbkjltLkTi1PJfTZ+TVSK GbTZc6VQfg9uLLEXicijgihsbWqCTycXWRLWagwiaB2YTIQmDpSScu8PJDj3L+2NZ9i4 vjDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=M6ruaLGEiw5B6IksG1Q4Y4RLvYCCrNywxBXb/mioalo=; b=CDXqHialJ7zNemh9rAlTMFfdZqe/5yykAPNdVy/IFIwpFpgb7OS26E2lSDCpUUIWaL bcKqdWROEx/MQyXlSSOhrnS5uP9DeZiUZ6RkoyWtiD1VS/9cSTSVMdmYuA1+Z9bJmsvH bCWR3r2tGKPPdIOy1JnvMyaVmUxB1guboteLLkoXU4A6NBh0oJ7O7wuTuA1uVl9norc0 Bu6eUyjwANEaLNUkM/qFRXnYR9v6RqsgjVW1j20/WSXlzB4KqtB8eDGYrqenycySd9RY 2Akc5tOkFupni9zVGjKRdTPKiBDwkJn6cLmQsDleI5pQF3KL3U1OEh0HIbAxAZm1Rg7Z ttzA== X-Gm-Message-State: AEkoouv58XcZiw0DH2jnVtGWQIXbG3+6FR187N7/N4uzhiD2+PuOctXbv/6uEaPGIWryLA== X-Received: by 10.194.173.74 with SMTP id bi10mr13948232wjc.72.1471272099029; Mon, 15 Aug 2016 07:41:39 -0700 (PDT) Received: from sixbynine.org ([192.198.151.62]) by smtp.gmail.com with ESMTPSA id d7sm21885161wjg.13.2016.08.15.07.41.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Aug 2016 07:41:38 -0700 (PDT) From: Robert Bragg To: intel-gfx@lists.freedesktop.org Date: Mon, 15 Aug 2016 15:41:21 +0100 Message-Id: <20160815144128.7847-5-robert@sixbynine.org> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20160815144128.7847-1-robert@sixbynine.org> References: <20160815144128.7847-1-robert@sixbynine.org> Cc: David Airlie , dri-devel@lists.freedesktop.org, Sourab Gupta , Daniel Vetter Subject: [Intel-gfx] [PATCH v3 04/11] drm/i915: don't whitelist oacontrol in cmd parser X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Being able to program OACONTROL from a non-privileged batch buffer is not sufficient to be able to configure the OA unit. This was originally allowed to help enable Mesa to expose OA counters via the INTEL_performance_query extension, but the current implementation based on programming OACONTROL via a batch buffer isn't able to report useable data without a more complete OA unit configuration. Mesa handles the possibility that writes to OACONTROL may not be allowed and so only advertises the extension after explicitly testing that a write to OACONTROL succeeds. Based on this; removing OACONTROL from the whitelist should be ok for userspace. Removing this simplifies adding a new kernel api for configuring the OA unit without needing to consider the possibility that userspace might trample on OACONTROL state which we'd like to start managing within the kernel instead. In particular running any Mesa based GL application currently results in clearing OACONTROL when initializing which would disable the capturing of metrics. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_cmd_parser.c | 38 ++-------------------------------- 1 file changed, 2 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 71e778b..ac03c71 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -446,7 +446,6 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = { REG64(PS_INVOCATION_COUNT), REG64(PS_DEPTH_COUNT), REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), - REG32(GEN7_OACONTROL), /* Only allowed for LRI and SRM. See below. */ REG64(MI_PREDICATE_SRC0), REG64(MI_PREDICATE_SRC1), REG32(GEN7_3DPRIM_END_OFFSET), @@ -1049,8 +1048,7 @@ bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine) static bool check_cmd(const struct intel_engine_cs *engine, const struct drm_i915_cmd_descriptor *desc, const u32 *cmd, u32 length, - const bool is_master, - bool *oacontrol_set) + const bool is_master) { if (desc->flags & CMD_DESC_REJECT) { DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); @@ -1088,31 +1086,6 @@ static bool check_cmd(const struct intel_engine_cs *engine, } /* - * OACONTROL requires some special handling for - * writes. We want to make sure that any batch which - * enables OA also disables it before the end of the - * batch. The goal is to prevent one process from - * snooping on the perf data from another process. To do - * that, we need to check the value that will be written - * to the register. Hence, limit OACONTROL writes to - * only MI_LOAD_REGISTER_IMM commands. - */ - if (reg_addr == i915_mmio_reg_offset(GEN7_OACONTROL)) { - if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { - DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n"); - return false; - } - - if (desc->cmd.value == MI_LOAD_REGISTER_REG) { - DRM_DEBUG_DRIVER("CMD: Rejected LRR to OACONTROL\n"); - return false; - } - - if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) - *oacontrol_set = (cmd[offset + 1] != 0); - } - - /* * Check the value written to the register against the * allowed mask/value pair given in the whitelist entry. */ @@ -1202,7 +1175,6 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, { u32 *cmd, *batch_base, *batch_end; struct drm_i915_cmd_descriptor default_desc = { 0 }; - bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */ int ret = 0; batch_base = copy_batch(shadow_batch_obj, batch_obj, @@ -1259,8 +1231,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, break; } - if (!check_cmd(engine, desc, cmd, length, is_master, - &oacontrol_set)) { + if (!check_cmd(engine, desc, cmd, length, is_master)) { ret = -EACCES; break; } @@ -1268,11 +1239,6 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, cmd += length; } - if (oacontrol_set) { - DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n"); - ret = -EINVAL; - } - if (cmd >= batch_end) { DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); ret = -EINVAL;