@@ -3554,6 +3554,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint8_t cpp;
uint32_t width = 0, height = 0;
uint32_t plane_pixel_rate;
+ uint32_t linetime_us = 0;
if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
*enabled = false;
@@ -3603,7 +3604,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
y_tile_minimum = plane_blocks_per_line * min_scanlines;
selected_result = max(method2, y_tile_minimum);
} else {
- if ((ddb_allocation / plane_blocks_per_line) >= 1)
+ linetime_us = DIV_ROUND_UP(width * 1000,
+ skl_pipe_pixel_rate(cstate));
+ if (latency >= linetime_us)
selected_result = min(method1, method2);
else
selected_result = method1;
This patch make changes to use linetime latency instead of allocated DDB size during plane watermark calculation in switch case, This is required to implement new DDB allocation algorithm. In New Algorithm DDB is allocated based on WM values, because of which number of DDB blocks will not be available during WM calculation, So this "linetime latency" is suggested by SV/HW team to use during switch-case for WM blocks selection. Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)