From patchwork Mon Aug 29 12:35:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Mahesh" X-Patchwork-Id: 9303879 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 50458607F0 for ; Mon, 29 Aug 2016 12:32:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4153D286C0 for ; Mon, 29 Aug 2016 12:32:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 35B972886B; Mon, 29 Aug 2016 12:32:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AD07B286C0 for ; Mon, 29 Aug 2016 12:32:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4BE546E53F; Mon, 29 Aug 2016 12:32:18 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6B7BA6E536 for ; Mon, 29 Aug 2016 12:32:06 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP; 29 Aug 2016 05:32:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.28,596,1464678000"; d="scan'208"; a="1042867619" Received: from kumarmah-desk.iind.intel.com ([10.223.26.44]) by orsmga002.jf.intel.com with ESMTP; 29 Aug 2016 05:32:04 -0700 From: "Kumar, Mahesh" To: intel-gfx@lists.freedesktop.org Date: Mon, 29 Aug 2016 18:05:22 +0530 Message-Id: <20160829123522.9532-8-mahesh1.kumar@intel.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160829123522.9532-1-mahesh1.kumar@intel.com> References: <20160829123522.9532-1-mahesh1.kumar@intel.com> Cc: Kumar@freedesktop.org Subject: [Intel-gfx] [PATCH] drm/i915/gen9: WM memory bandwidth related workaround X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch implemnets Workariunds related to display arbitrated memory bandwidth. These WA are applicabe for all gen-9 based platforms. Signed-off-by: Kumar, Mahesh --- drivers/gpu/drm/i915/i915_drv.h | 9 +++ drivers/gpu/drm/i915/intel_drv.h | 11 +++ drivers/gpu/drm/i915/intel_pm.c | 145 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d0123f8..095af6c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1055,6 +1055,13 @@ enum intel_sbi_destination { SBI_MPHY, }; +/* SKL+ Watermark arbitrated display bandwidth Workarounds */ +enum watermark_memory_wa { + WATERMARK_WA_NONE, + WATERMARK_WA_X_TILED, + WATERMARK_WA_Y_TILED, +}; + #define QUIRK_PIPEA_FORCE (1<<0) #define QUIRK_LVDS_SSC_DISABLE (1<<1) #define QUIRK_INVERT_BRIGHTNESS (1<<2) @@ -1604,6 +1611,8 @@ struct skl_ddb_allocation { struct skl_wm_values { unsigned dirty_pipes; + /* any WaterMark memory workaround Required */ + enum watermark_memory_wa mem_wa; struct skl_ddb_allocation ddb; uint32_t wm_linetime[I915_MAX_PIPES]; uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 570a7ca..f2c38cc 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1807,6 +1807,17 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state, return to_intel_crtc_state(crtc_state); } +static inline struct intel_crtc_state * +intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state, + struct intel_crtc *crtc) +{ + struct drm_crtc_state *crtc_state; + + crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base); + + return to_intel_crtc_state(crtc_state); +} + static inline struct intel_plane_state * intel_atomic_get_existing_plane_state(struct drm_atomic_state *state, struct intel_plane *plane) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ac0d0ca..e9cd6ac 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3624,6 +3624,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, { struct drm_plane_state *pstate = &intel_pstate->base; struct drm_framebuffer *fb = pstate->fb; + struct intel_atomic_state *intel_state = + to_intel_atomic_state(cstate->base.state); uint32_t latency = dev_priv->wm.skl_latency[level]; uint32_t method1, method2; uint32_t plane_bytes_per_line, plane_blocks_per_line; @@ -3639,10 +3641,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, uint8_t *out_lines = &result->plane_res_l[id]; uint32_t y_tile_minimum = 0; bool y_tile = false; + enum watermark_memory_wa mem_wa; if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) return 0; + mem_wa = intel_state ? intel_state->wm_results.mem_wa : WATERMARK_WA_NONE; + if (mem_wa != WATERMARK_WA_NONE) { + if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) + latency += 15; + } + width = drm_rect_width(&intel_pstate->base.src) >> 16; height = drm_rect_height(&intel_pstate->base.src) >> 16; @@ -3682,6 +3691,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, WARN(1, "Unsupported pixel depth for rotation"); } } + if (mem_wa == WATERMARK_WA_Y_TILED) + min_scanlines *= 2; + y_tile_minimum = plane_blocks_per_line * min_scanlines; selected_result = max(method2, y_tile_minimum); y_tile = true; @@ -4065,6 +4077,15 @@ skl_include_affected_pipes(struct drm_atomic_state *state) intel_state->wm_results.dirty_pipes = ~0; } + /* + * If Watermark workaround is changed we need to recalculate + * watermark values for all active pipes + */ + if (intel_state->wm_results.mem_wa != dev_priv->wm.skl_hw.mem_wa) { + realloc_pipes = ~0; + intel_state->wm_results.dirty_pipes = ~0; + } + for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) { struct intel_crtc_state *cstate; @@ -4081,6 +4102,128 @@ skl_include_affected_pipes(struct drm_atomic_state *state) } static void +skl_set_memory_bandwidth_wm_wa(struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *intel_crtc; + struct intel_plane_state *intel_pstate; + struct intel_atomic_state *intel_state = to_intel_atomic_state(state); + int num_active_plane, num_active_pipe; + uint32_t plane_bw, max_plane_bw, pipe_bw, max_pipe_bw; + uint32_t total_pipe_bw; + uint32_t system_bw = 0; + uint8_t num_channel, data_width, rank; + int x_tile_per; + int display_bw_per; + bool y_tile_enabled = false; + + if (!dev_priv->memdev_info.valid) + goto exit; + + num_channel = dev_priv->memdev_info.num_channel; + data_width = dev_priv->memdev_info.data_width; + system_bw = dev_priv->memdev_info.mem_speed * num_channel * data_width; + + if (!system_bw) + goto exit; + + max_pipe_bw = 0; + for_each_intel_crtc(dev, intel_crtc) { + struct intel_crtc_state *cstate; + struct intel_plane *plane; + + /* + * If CRTC is part of current atomic commit, get crtc state from + * existing CRTC state. else take the cached CRTC state + */ + cstate = NULL; + if (state) + cstate = intel_atomic_get_existing_crtc_state(state, + intel_crtc); + if (!cstate) + cstate = to_intel_crtc_state(intel_crtc->base.state); + + if (!cstate->base.active) + continue; + + num_active_plane = 0; + max_plane_bw = 0; + for_each_intel_plane_mask(dev, plane, cstate->base.plane_mask) { + struct drm_framebuffer *fb = NULL; + + intel_pstate = NULL; + if (state) + intel_pstate = + intel_atomic_get_existing_plane_state(state, + plane); + if (!intel_pstate) + intel_pstate = + to_intel_plane_state(plane->base.state); + + WARN_ON(!intel_pstate->base.fb); + + if (!intel_pstate->base.visible) + continue; + + fb = intel_pstate->base.fb; + if (fb && (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || + fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)) + y_tile_enabled = true; + + plane_bw = skl_adjusted_plane_pixel_rate(cstate, + intel_pstate); + max_plane_bw = max(plane_bw, max_plane_bw); + num_active_plane++; + } + pipe_bw = max_plane_bw * num_active_plane; + max_pipe_bw = max(pipe_bw, max_pipe_bw); + } + + if (intel_state->active_pipe_changes) + num_active_pipe = hweight32(intel_state->active_crtcs); + else + num_active_pipe = hweight32(dev_priv->active_crtcs); + + total_pipe_bw = max_pipe_bw * num_active_pipe; + + display_bw_per = DIV_ROUND_UP_ULL(total_pipe_bw * 100, system_bw * 1000); + + /* + * If there is any Ytile plane enabled and arbitrated display + * bandwidth > 20% of raw system memory bandwidth + * Enale Y-tile related WA + * + * If memory is dual channel single rank, Xtile limit = 35%, else Xtile + * limit = 60% + * If there is no Ytile plane enabled and + * arbitrated display bandwidth > Xtile limit + * Enable X-tile realated WA + */ + if (y_tile_enabled && (display_bw_per > 20)) + intel_state->wm_results.mem_wa = WATERMARK_WA_Y_TILED; + else { + + if (dev_priv->memdev_info.rank_valid) + rank = dev_priv->memdev_info.rank; + else + rank = DRAM_DUAL_RANK; /* Assume we are dual rank */ + + if ((rank == DRAM_SINGLE_RANK) && (num_channel == 2)) + x_tile_per = 35; + else + x_tile_per = 60; + + if (display_bw_per > x_tile_per) + intel_state->wm_results.mem_wa = WATERMARK_WA_X_TILED; + } + return; + +exit: + intel_state->wm_results.mem_wa = WATERMARK_WA_NONE; +} + +static void skl_copy_wm_for_pipe(struct skl_wm_values *dst, struct skl_wm_values *src, enum pipe pipe) @@ -4125,6 +4268,8 @@ skl_compute_wm(struct drm_atomic_state *state) /* Clear all dirty flags */ results->dirty_pipes = 0; + skl_set_memory_bandwidth_wm_wa(state); + ret = skl_include_affected_pipes(state); if (ret) return ret;