From patchwork Thu Sep 8 11:26:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Kumar, Mahesh" X-Patchwork-Id: 9321041 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EB9D460752 for ; Thu, 8 Sep 2016 11:22:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E0FE5297E2 for ; Thu, 8 Sep 2016 11:22:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D5BF9297E5; Thu, 8 Sep 2016 11:22:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 42F9F297E2 for ; Thu, 8 Sep 2016 11:22:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 88AF46E12F; Thu, 8 Sep 2016 11:22:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id CD81C6E153 for ; Thu, 8 Sep 2016 11:22:48 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 08 Sep 2016 04:22:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.30,300,1470726000"; d="scan'208"; a="1026831903" Received: from kumarmah-desk.iind.intel.com ([10.223.26.44]) by orsmga001.jf.intel.com with ESMTP; 08 Sep 2016 04:22:46 -0700 From: "Kumar, Mahesh" To: intel-gfx@lists.freedesktop.org Date: Thu, 8 Sep 2016 16:56:34 +0530 Message-Id: <20160908112634.14957-10-mahesh1.kumar@intel.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160908112634.14957-1-mahesh1.kumar@intel.com> References: <20160829123522.9532-1-mahesh1.kumar@intel.com> <20160908112634.14957-1-mahesh1.kumar@intel.com> MIME-Version: 1.0 Cc: paulo.r.zanoni@intel.com Subject: [Intel-gfx] [PATCH v2 9/9] drm/i915/bxt: Implement Transition WM X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Mahesh Kumar This patch enables Transition WM for SKL+ platforms. Transition WM are used if IPC is enabled, to decide, number of blocks to be fetched before reducing the priority of display to fetch from memory. Changes since v1: - Don't enable transition WM for GEN9 (Art/Paulo) - Rebase to use fixed point 16.16 calculation - Fix the use of selected result from latency level-0 Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 60 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 57 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8d0037c..f6a3fab 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2862,6 +2862,8 @@ bool ilk_disable_lp_wm(struct drm_device *dev) #define SKL_DDB_SIZE 896 /* in blocks */ #define BXT_DDB_SIZE 512 +#define SKL_TRANS_WM_AMOUNT 10 /* tunable value */ +#define SKL_TRANS_WM_MIN 14 #define SKL_SAGV_BLOCK_TIME 30 /* µs */ /* @@ -3583,6 +3585,48 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst return pixel_rate; } +static void skl_compute_plane_trans_wm(const struct drm_i915_private *dev_priv, + struct skl_pipe_wm *pipe_wm, + struct intel_plane_state *intel_pstate, + uint32_t selected_result, + uint32_t y_tile_min, + bool y_tile) +{ + struct drm_plane_state *pstate = &intel_pstate->base; + int id = skl_wm_plane_id(to_intel_plane(pstate->plane)); + uint16_t *out_blocks = &pipe_wm->trans_wm.plane_res_b[id]; + uint8_t *out_lines = &pipe_wm->trans_wm.plane_res_l[id]; + uint32_t trans_min = 0, trans_offset_blocks; + uint32_t trans_y_tile_min = 0, res_blocks = 0; + uint16_t trans_res_blocks = 0; + + /* Keep Trans WM disabled for GEN9 */ + if (IS_GEN9(dev_priv)) + goto exit; + + trans_min = SKL_TRANS_WM_MIN; + + trans_offset_blocks = (trans_min + SKL_TRANS_WM_AMOUNT) << 16; + + if (y_tile) { + trans_y_tile_min = 2 * y_tile_min; + res_blocks = max(trans_y_tile_min, selected_result) + + trans_offset_blocks; + } else { + res_blocks = selected_result + trans_offset_blocks; + } + + trans_res_blocks = DIV_ROUND_UP(res_blocks, 1 << 16) + 1; + + /* WA BUG:1938466 add one block for non y-tile planes */ + if (!y_tile) + trans_res_blocks += 1; +exit: + *out_blocks = trans_res_blocks; + *out_lines = 0; +} + + static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, struct intel_crtc_state *cstate, struct intel_plane_state *intel_pstate, @@ -3709,6 +3753,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, *out_blocks = res_blocks; *out_lines = res_lines; + if (level == 0) + skl_compute_plane_trans_wm(dev_priv, pipe_wm, intel_pstate, + selected_result, y_tile_minimum, y_tiled); return 0; } @@ -3778,11 +3825,13 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate) } static void skl_compute_transition_wm(struct intel_crtc_state *cstate, - struct skl_wm_level *trans_wm /* out */) + struct skl_wm_level *trans_wm, /* out */ + struct skl_ddb_allocation *ddb) { struct drm_crtc *crtc = cstate->base.crtc; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_plane *intel_plane; + enum pipe pipe = to_intel_crtc(crtc)->pipe; if (!cstate->base.active) return; @@ -3790,8 +3839,13 @@ static void skl_compute_transition_wm(struct intel_crtc_state *cstate, /* Until we know more, just disable transition WMs */ for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) { int i = skl_wm_plane_id(intel_plane); + uint16_t plane_ddb = skl_ddb_entry_size(&ddb->plane[pipe][i]); + uint16_t trans_res_blocks = trans_wm->plane_res_b[i]; - trans_wm->plane_en[i] = false; + if ((plane_ddb > 0) && (trans_res_blocks > plane_ddb)) + trans_wm->plane_en[i] = false; + else + trans_wm->plane_en[i] = true; } } @@ -3822,7 +3876,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, pipe_wm->linetime = skl_compute_linetime_wm(cstate); - skl_compute_transition_wm(cstate, &pipe_wm->trans_wm); + skl_compute_transition_wm(cstate, &pipe_wm->trans_wm, ddb); return 0; }