From patchwork Thu Sep 8 11:26:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Mahesh" X-Patchwork-Id: 9321025 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 89F42607D3 for ; Thu, 8 Sep 2016 11:22:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7ECF0297E0 for ; Thu, 8 Sep 2016 11:22:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 72FAA297E3; Thu, 8 Sep 2016 11:22:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 24E54297E2 for ; Thu, 8 Sep 2016 11:22:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 94D296E0D9; Thu, 8 Sep 2016 11:22:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id E4BCA6E0EB for ; Thu, 8 Sep 2016 11:22:27 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 08 Sep 2016 04:22:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.30,300,1470726000"; d="scan'208"; a="1026831735" Received: from kumarmah-desk.iind.intel.com ([10.223.26.44]) by orsmga001.jf.intel.com with ESMTP; 08 Sep 2016 04:22:26 -0700 From: "Kumar, Mahesh" To: intel-gfx@lists.freedesktop.org Date: Thu, 8 Sep 2016 16:56:26 +0530 Message-Id: <20160908112634.14957-2-mahesh1.kumar@intel.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160908112634.14957-1-mahesh1.kumar@intel.com> References: <20160829123522.9532-1-mahesh1.kumar@intel.com> <20160908112634.14957-1-mahesh1.kumar@intel.com> Cc: paulo.r.zanoni@intel.com Subject: [Intel-gfx] [PATCH v2 1/9] drm/i915/skl: pass pipe_wm in skl_compute_(wm_level/plane_wm) functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Mahesh Kumar This patch make use of plane_wm variable directly instead of passing skl_plane_wm struct. this way reduces number of argument requirement in watermark calculation functions. It also gives more freedom of decision making to implement Bspec WM workarounds. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 86c6d66..3fdec4d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3542,9 +3542,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, struct intel_plane_state *intel_pstate, uint16_t ddb_allocation, int level, - uint16_t *out_blocks, /* out */ - uint8_t *out_lines, /* out */ - bool *enabled /* out */) + struct skl_pipe_wm *pipe_wm) { struct drm_plane_state *pstate = &intel_pstate->base; struct drm_framebuffer *fb = pstate->fb; @@ -3557,6 +3555,11 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, uint32_t width = 0, height = 0; uint32_t plane_pixel_rate; uint32_t y_tile_minimum, y_min_scanlines; + int id = skl_wm_plane_id(to_intel_plane(pstate->plane)); + struct skl_wm_level *result = &pipe_wm->wm[level]; + uint16_t *out_blocks = &result->plane_res_b[id]; + uint8_t *out_lines = &result->plane_res_l[id]; + bool *enabled = &result->plane_en[id]; if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) { *enabled = false; @@ -3673,7 +3676,7 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv, struct skl_ddb_allocation *ddb, struct intel_crtc_state *cstate, int level, - struct skl_wm_level *result) + struct skl_pipe_wm *pipe_wm) { struct drm_atomic_state *state = cstate->base.state; struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); @@ -3684,12 +3687,6 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv, enum pipe pipe = intel_crtc->pipe; int ret; - /* - * We'll only calculate watermarks for planes that are actually - * enabled, so make sure all other planes are set as disabled. - */ - memset(result, 0, sizeof(*result)); - for_each_intel_plane_mask(&dev_priv->drm, intel_plane, cstate->base.plane_mask) { @@ -3727,9 +3724,7 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv, intel_pstate, ddb_blocks, level, - &result->plane_res_b[i], - &result->plane_res_l[i], - &result->plane_en[i]); + pipe_wm); if (ret) return ret; } @@ -3777,9 +3772,15 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, int level, max_level = ilk_wm_max_level(dev); int ret; + /* + * We'll only calculate watermarks for planes that are actually + * enabled, so make sure all other planes are set as disabled. + */ + memset(pipe_wm, 0, sizeof(*pipe_wm)); + for (level = 0; level <= max_level; level++) { ret = skl_compute_wm_level(dev_priv, ddb, cstate, - level, &pipe_wm->wm[level]); + level, pipe_wm); if (ret) return ret; }