From patchwork Thu Sep 8 11:26:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Mahesh" X-Patchwork-Id: 9321039 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3E9D360752 for ; Thu, 8 Sep 2016 11:22:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 34A72297E2 for ; Thu, 8 Sep 2016 11:22:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 294A5297E6; Thu, 8 Sep 2016 11:22:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BC574297E3 for ; Thu, 8 Sep 2016 11:22:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 382C66E12A; Thu, 8 Sep 2016 11:22:48 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 79F8F6E12F for ; Thu, 8 Sep 2016 11:22:46 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 08 Sep 2016 04:22:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.30,300,1470726000"; d="scan'208"; a="1026831878" Received: from kumarmah-desk.iind.intel.com ([10.223.26.44]) by orsmga001.jf.intel.com with ESMTP; 08 Sep 2016 04:22:44 -0700 From: "Kumar, Mahesh" To: intel-gfx@lists.freedesktop.org Date: Thu, 8 Sep 2016 16:56:33 +0530 Message-Id: <20160908112634.14957-9-mahesh1.kumar@intel.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160908112634.14957-1-mahesh1.kumar@intel.com> References: <20160829123522.9532-1-mahesh1.kumar@intel.com> <20160908112634.14957-1-mahesh1.kumar@intel.com> Cc: paulo.r.zanoni@intel.com Subject: [Intel-gfx] [PATCH v2 8/9] drm/i915/bxt: set chicken bit as IPC y-tile WA X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Mahesh Kumar It implements the WA to enable IDLE_WAKEMEM bit of CHICKEN_DCPR_1 register for Broxton platform. When IPC is enabled & Y-tile is enabled in any of the enabled plane, above bit should be set. Without this WA system observes random hang. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7964c0f..c94eedb 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1619,6 +1619,8 @@ struct skl_wm_values { unsigned dirty_pipes; /* any WaterMark memory workaround Required */ enum watermark_memory_wa mem_wa; + /* IPC Y-tiled WA related member */ + u32 y_plane_mask; struct skl_ddb_allocation ddb; uint32_t wm_linetime[I915_MAX_PIPES]; uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 75b5b52..210d9b0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5658,6 +5658,9 @@ enum { #define PLANE_NV12_BUF_CFG(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) +#define CHICKEN_DCPR_1 _MMIO(0x46430) +#define IDLE_WAKEMEM_MASK (1 << 13) + /* SKL new cursor registers */ #define _CUR_BUF_CFG_A 0x7017c #define _CUR_BUF_CFG_B 0x7117c diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a6c3caa..c75685d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12429,6 +12429,8 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, bool is_crtc_enabled = crtc_state->active; bool turn_off, turn_on, visible, was_visible; struct drm_framebuffer *fb = plane_state->fb; + struct intel_atomic_state *intel_state = + to_intel_atomic_state(plane_state->state); int ret; if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { @@ -12515,6 +12517,15 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, !needs_scaling(old_plane_state)) pipe_config->disable_lp_wm = true; + if (fb && (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || + fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)) { + intel_state->wm_results.y_plane_mask |= + (1 << drm_plane_index(plane)); + } else { + intel_state->wm_results.y_plane_mask &= + ~(1 << drm_plane_index(plane)); + } + return 0; } @@ -13985,6 +13996,10 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) return ret; + /* Copy the Y-tile WA related states */ + intel_state->wm_results.y_plane_mask = + dev_priv->wm.skl_results.y_plane_mask; + for_each_crtc_in_state(state, crtc, crtc_state, i) { struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); @@ -14226,6 +14241,32 @@ static void intel_update_crtcs(struct drm_atomic_state *state, } } +/* + * GEN9 IPC WA for Y-tiled + */ +void bxt_set_ipc_wa(struct drm_i915_private *dev_priv, bool enable) +{ + u32 val; + + if (!IS_BROXTON(dev_priv) || !i915.enable_ipc) + return; + + val = I915_READ(CHICKEN_DCPR_1); + /* + * If WA is already enabled or disabled + * no need to re-enable or disable it. + */ + if ((enable && (val & IDLE_WAKEMEM_MASK)) || + (!enable && !(val & IDLE_WAKEMEM_MASK))) + return; + + if (enable) + val |= IDLE_WAKEMEM_MASK; + else + val &= ~IDLE_WAKEMEM_MASK; + I915_WRITE(CHICKEN_DCPR_1, val); +} + static void skl_update_crtcs(struct drm_atomic_state *state, unsigned int *crtc_vblank_mask) { @@ -14241,6 +14282,12 @@ static void skl_update_crtcs(struct drm_atomic_state *state, enum pipe pipe; /* + * If IPC WA need to be enabled, enable it now + */ + if (intel_state->wm_results.y_plane_mask) + bxt_set_ipc_wa(dev_priv, true); + + /* * Whenever the number of active pipes changes, we need to make sure we * update the pipes in the right order so that their ddb allocations * never overlap with eachother inbetween CRTC updates. Otherwise we'll @@ -14283,6 +14330,9 @@ static void skl_update_crtcs(struct drm_atomic_state *state, progress = true; } } while (progress); + + if (!intel_state->wm_results.y_plane_mask) + bxt_set_ipc_wa(dev_priv, false); } static void intel_atomic_commit_tail(struct drm_atomic_state *state)