| Message ID | 20160914115423.6349-1-mahesh1.kumar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Em Qua, 2016-09-14 às 17:24 +0530, Kumar, Mahesh escreveu: > From: Mahesh Kumar <mahesh1.kumar@intel.com> > > This patch enables Transition WM for SKL+ platforms. > > Transition WM are used if IPC is enabled, to decide, number of blocks > to be fetched before reducing the priority of display to fetch from > memory. > > Changes since v1: > - Don't enable transition WM for GEN9 (Art/Paulo) > - Rebase to use fixed point 16.16 calculation > - Fix the use of selected result from latency level-0 > > Changes since v2: > - Fix transition WM enable condition > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 60 > ++++++++++++++++++++++++++++++++++++++--- > 1 file changed, 57 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c > index de2e738..4814a1a 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2862,6 +2862,8 @@ bool ilk_disable_lp_wm(struct drm_device *dev) > > #define SKL_DDB_SIZE 896 /* in blocks */ > #define BXT_DDB_SIZE 512 > +#define SKL_TRANS_WM_AMOUNT 10 /* tunable value */ > +#define SKL_TRANS_WM_MIN 14 > #define SKL_SAGV_BLOCK_TIME 30 /* µs */ > > /* > @@ -3583,6 +3585,48 @@ static uint32_t > skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst > return pixel_rate; > } > > +static void skl_compute_plane_trans_wm(const struct drm_i915_private > *dev_priv, > + struct skl_pipe_wm *pipe_wm, > + struct intel_plane_state > *intel_pstate, > + uint32_t selected_result, > + uint32_t y_tile_min, > + bool y_tile) > +{ > + struct drm_plane_state *pstate = &intel_pstate->base; > + int id = skl_wm_plane_id(to_intel_plane(pstate->plane)); > + uint16_t *out_blocks = &pipe_wm->trans_wm.plane_res_b[id]; > + uint8_t *out_lines = &pipe_wm->trans_wm.plane_res_l[id]; > + uint32_t trans_min = 0, trans_offset_blocks; > + uint32_t trans_y_tile_min = 0, res_blocks = 0; > + uint16_t trans_res_blocks = 0; > + > + /* Keep Trans WM disabled for GEN9 */ > + if (IS_GEN9(dev_priv)) > + goto exit; But the only platforms that call this function are gen9... > + > + trans_min = SKL_TRANS_WM_MIN; > + > + trans_offset_blocks = (trans_min + SKL_TRANS_WM_AMOUNT) << > 16; > + > + if (y_tile) { > + trans_y_tile_min = 2 * y_tile_min; > + res_blocks = max(trans_y_tile_min, selected_result) > + > + trans_offset_blocks; > + } else { > + res_blocks = selected_result + trans_offset_blocks; > + } > + > + trans_res_blocks = DIV_ROUND_UP(res_blocks, 1 << 16) + 1; > + > + /* WA BUG:1938466 add one block for non y-tile planes */ > + if (!y_tile) > + trans_res_blocks += 1; > +exit: > + *out_blocks = trans_res_blocks; > + *out_lines = 0; > +} > + > + > static int skl_compute_plane_wm(const struct drm_i915_private > *dev_priv, > struct intel_crtc_state *cstate, > struct intel_plane_state > *intel_pstate, > @@ -3709,6 +3753,9 @@ static int skl_compute_plane_wm(const struct > drm_i915_private *dev_priv, > *out_blocks = res_blocks; > *out_lines = res_lines; > > + if (level == 0) > + skl_compute_plane_trans_wm(dev_priv, pipe_wm, > intel_pstate, > + selected_result, y_tile_minimum, > y_tiled); > return 0; > } > > @@ -3778,11 +3825,13 @@ skl_compute_linetime_wm(struct > intel_crtc_state *cstate) > } > > static void skl_compute_transition_wm(struct intel_crtc_state > *cstate, > - struct skl_wm_level *trans_wm > /* out */) > + struct skl_wm_level *trans_wm, > /* out */ > + struct skl_ddb_allocation > *ddb) > { > struct drm_crtc *crtc = cstate->base.crtc; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > struct intel_plane *intel_plane; > + enum pipe pipe = to_intel_crtc(crtc)->pipe; > > if (!cstate->base.active) > return; > @@ -3790,8 +3839,13 @@ static void skl_compute_transition_wm(struct > intel_crtc_state *cstate, > /* Until we know more, just disable transition WMs */ > for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, > intel_plane) { > int i = skl_wm_plane_id(intel_plane); > + uint16_t plane_ddb = skl_ddb_entry_size(&ddb- > >plane[pipe][i]); > + uint16_t trans_res_blocks = trans_wm- > >plane_res_b[i]; > > - trans_wm->plane_en[i] = false; > + if ((trans_res_blocks > 0) && (trans_res_blocks <= > plane_ddb)) > + trans_wm->plane_en[i] = true; > + else > + trans_wm->plane_en[i] = false; > } > } > > @@ -3822,7 +3876,7 @@ static int skl_build_pipe_wm(struct > intel_crtc_state *cstate, > > pipe_wm->linetime = skl_compute_linetime_wm(cstate); > > - skl_compute_transition_wm(cstate, &pipe_wm->trans_wm); > + skl_compute_transition_wm(cstate, &pipe_wm->trans_wm, ddb); > > return 0; > }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index de2e738..4814a1a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2862,6 +2862,8 @@ bool ilk_disable_lp_wm(struct drm_device *dev) #define SKL_DDB_SIZE 896 /* in blocks */ #define BXT_DDB_SIZE 512 +#define SKL_TRANS_WM_AMOUNT 10 /* tunable value */ +#define SKL_TRANS_WM_MIN 14 #define SKL_SAGV_BLOCK_TIME 30 /* µs */ /* @@ -3583,6 +3585,48 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst return pixel_rate; } +static void skl_compute_plane_trans_wm(const struct drm_i915_private *dev_priv, + struct skl_pipe_wm *pipe_wm, + struct intel_plane_state *intel_pstate, + uint32_t selected_result, + uint32_t y_tile_min, + bool y_tile) +{ + struct drm_plane_state *pstate = &intel_pstate->base; + int id = skl_wm_plane_id(to_intel_plane(pstate->plane)); + uint16_t *out_blocks = &pipe_wm->trans_wm.plane_res_b[id]; + uint8_t *out_lines = &pipe_wm->trans_wm.plane_res_l[id]; + uint32_t trans_min = 0, trans_offset_blocks; + uint32_t trans_y_tile_min = 0, res_blocks = 0; + uint16_t trans_res_blocks = 0; + + /* Keep Trans WM disabled for GEN9 */ + if (IS_GEN9(dev_priv)) + goto exit; + + trans_min = SKL_TRANS_WM_MIN; + + trans_offset_blocks = (trans_min + SKL_TRANS_WM_AMOUNT) << 16; + + if (y_tile) { + trans_y_tile_min = 2 * y_tile_min; + res_blocks = max(trans_y_tile_min, selected_result) + + trans_offset_blocks; + } else { + res_blocks = selected_result + trans_offset_blocks; + } + + trans_res_blocks = DIV_ROUND_UP(res_blocks, 1 << 16) + 1; + + /* WA BUG:1938466 add one block for non y-tile planes */ + if (!y_tile) + trans_res_blocks += 1; +exit: + *out_blocks = trans_res_blocks; + *out_lines = 0; +} + + static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, struct intel_crtc_state *cstate, struct intel_plane_state *intel_pstate, @@ -3709,6 +3753,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, *out_blocks = res_blocks; *out_lines = res_lines; + if (level == 0) + skl_compute_plane_trans_wm(dev_priv, pipe_wm, intel_pstate, + selected_result, y_tile_minimum, y_tiled); return 0; } @@ -3778,11 +3825,13 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate) } static void skl_compute_transition_wm(struct intel_crtc_state *cstate, - struct skl_wm_level *trans_wm /* out */) + struct skl_wm_level *trans_wm, /* out */ + struct skl_ddb_allocation *ddb) { struct drm_crtc *crtc = cstate->base.crtc; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_plane *intel_plane; + enum pipe pipe = to_intel_crtc(crtc)->pipe; if (!cstate->base.active) return; @@ -3790,8 +3839,13 @@ static void skl_compute_transition_wm(struct intel_crtc_state *cstate, /* Until we know more, just disable transition WMs */ for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) { int i = skl_wm_plane_id(intel_plane); + uint16_t plane_ddb = skl_ddb_entry_size(&ddb->plane[pipe][i]); + uint16_t trans_res_blocks = trans_wm->plane_res_b[i]; - trans_wm->plane_en[i] = false; + if ((trans_res_blocks > 0) && (trans_res_blocks <= plane_ddb)) + trans_wm->plane_en[i] = true; + else + trans_wm->plane_en[i] = false; } } @@ -3822,7 +3876,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, pipe_wm->linetime = skl_compute_linetime_wm(cstate); - skl_compute_transition_wm(cstate, &pipe_wm->trans_wm); + skl_compute_transition_wm(cstate, &pipe_wm->trans_wm, ddb); return 0; }