From patchwork Wed Sep 14 14:19:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Bragg X-Patchwork-Id: 9331661 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AC902608A0 for ; Wed, 14 Sep 2016 14:21:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E406288B3 for ; Wed, 14 Sep 2016 14:21:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 934D829EEF; Wed, 14 Sep 2016 14:21:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F0EED29E80 for ; Wed, 14 Sep 2016 14:21:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B9F56E75D; Wed, 14 Sep 2016 14:20:46 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3C5546E745; Wed, 14 Sep 2016 14:20:18 +0000 (UTC) Received: by mail-wm0-x244.google.com with SMTP id b187so2788172wme.0; Wed, 14 Sep 2016 07:20:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=I+nzD+mvzREmWX4WEd7gmjl+26RQbybko2xGkDmTUbs=; b=CfoP4SVA1aSgztfXewFwg1x29CKE1mrBhDGkt/RU9H27wfp5wogqbQlkM1m1QLFzgN jYjoYneClRP7/wIIn0cPZtVDpYVPxWLLa9iWe87zPXiq84wCUVYj94Y6+RimrY9ogjeA Fw5XwWBZ6fWsmqYMVe0SJwySWoWPrSWoSanYmzZohBu31pJtjdfQ9tXox8Ll0ywVJ8f+ WikpeZar9zKF/BrNahIKtSVteh5O91WOPLwVuIFmiarzYWFnmC7t16XZZj4L5oW0DtcJ kwNiWIjef43RTQvfnoRPNOcX8TDN1yaxvdMB4kWh20I6OJ8TUCXU5YPFm86nOWN6nPWl 8SKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=I+nzD+mvzREmWX4WEd7gmjl+26RQbybko2xGkDmTUbs=; b=L//hMbS9xqHgtvqH/JEIc8FQ335gISzrp9h6IixgQMVhzJxTYc0ia02nq2anmERI/8 toYAkSIaJOEcI3/od0guvuaOvH4g0vpP61tG3uzn/iMC6S61aYN+ZaEiwlq4yDwf1kZF Tpcp01MIQcZZ7yyVWTL4FR2bqXWJA4Hkczba5RujhwGdkcRbRUvFhKnfceMRCqj775Oe Dten0w4caRdePlOj8UyL8NFlE1AEvj/pERLl0zIaxXNza0O2DBYDlQovhBJBQ38BHD7v HDdaaoQrEAz+1Dy0kSAZq3hE0hnEmq8TiHQ/ZhIhMr/N4JTh7rOySMSxtKhcEn39ATrQ cRuw== X-Gm-Message-State: AE9vXwNLnMqDWf2jfKID6e2KxN30qhZZc9YyGdesKXHTgl/jmzMO2R0H3UWFYCTwAyjE9g== X-Received: by 10.194.191.162 with SMTP id gz2mr2785265wjc.182.1473862816114; Wed, 14 Sep 2016 07:20:16 -0700 (PDT) Received: from sixbynine.org (host-78-151-16-234.as13285.net. [78.151.16.234]) by smtp.gmail.com with ESMTPSA id v189sm11014424wmv.12.2016.09.14.07.20.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 14 Sep 2016 07:20:15 -0700 (PDT) From: Robert Bragg To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Sep 2016 15:19:42 +0100 Message-Id: <20160914141949.27402-5-robert@sixbynine.org> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20160914141949.27402-1-robert@sixbynine.org> References: <20160914141949.27402-1-robert@sixbynine.org> Cc: David Airlie , dri-devel@lists.freedesktop.org, Sourab Gupta , Daniel Vetter Subject: [Intel-gfx] [PATCH v5 04/11] drm/i915: don't whitelist oacontrol in cmd parser X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Being able to program OACONTROL from a non-privileged batch buffer is not sufficient to be able to configure the OA unit. This was originally allowed to help enable Mesa to expose OA counters via the INTEL_performance_query extension, but the current implementation based on programming OACONTROL via a batch buffer isn't able to report useable data without a more complete OA unit configuration. Mesa handles the possibility that writes to OACONTROL may not be allowed and so only advertises the extension after explicitly testing that a write to OACONTROL succeeds. Based on this; removing OACONTROL from the whitelist should be ok for userspace. Removing this simplifies adding a new kernel api for configuring the OA unit without needing to consider the possibility that userspace might trample on OACONTROL state which we'd like to start managing within the kernel instead. In particular running any Mesa based GL application currently results in clearing OACONTROL when initializing which would disable the capturing of metrics. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_cmd_parser.c | 38 ++-------------------------------- 1 file changed, 2 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 5ad02dc..bdee590 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -450,7 +450,6 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = { REG64(PS_INVOCATION_COUNT), REG64(PS_DEPTH_COUNT), REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), - REG32(GEN7_OACONTROL), /* Only allowed for LRI and SRM. See below. */ REG64(MI_PREDICATE_SRC0), REG64(MI_PREDICATE_SRC1), REG32(GEN7_3DPRIM_END_OFFSET), @@ -1060,8 +1059,7 @@ bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine) static bool check_cmd(const struct intel_engine_cs *engine, const struct drm_i915_cmd_descriptor *desc, const u32 *cmd, u32 length, - const bool is_master, - bool *oacontrol_set) + const bool is_master) { if (desc->flags & CMD_DESC_SKIP) return true; @@ -1099,31 +1097,6 @@ static bool check_cmd(const struct intel_engine_cs *engine, } /* - * OACONTROL requires some special handling for - * writes. We want to make sure that any batch which - * enables OA also disables it before the end of the - * batch. The goal is to prevent one process from - * snooping on the perf data from another process. To do - * that, we need to check the value that will be written - * to the register. Hence, limit OACONTROL writes to - * only MI_LOAD_REGISTER_IMM commands. - */ - if (reg_addr == i915_mmio_reg_offset(GEN7_OACONTROL)) { - if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { - DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n"); - return false; - } - - if (desc->cmd.value == MI_LOAD_REGISTER_REG) { - DRM_DEBUG_DRIVER("CMD: Rejected LRR to OACONTROL\n"); - return false; - } - - if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) - *oacontrol_set = (cmd[offset + 1] != 0); - } - - /* * Check the value written to the register against the * allowed mask/value pair given in the whitelist entry. */ @@ -1214,7 +1187,6 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, u32 *cmd, *batch_end; struct drm_i915_cmd_descriptor default_desc = noop_desc; const struct drm_i915_cmd_descriptor *desc = &default_desc; - bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */ bool needs_clflush_after = false; int ret = 0; @@ -1270,8 +1242,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, break; } - if (!check_cmd(engine, desc, cmd, length, is_master, - &oacontrol_set)) { + if (!check_cmd(engine, desc, cmd, length, is_master)) { ret = -EACCES; break; } @@ -1279,11 +1250,6 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, cmd += length; } - if (oacontrol_set) { - DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n"); - ret = -EINVAL; - } - if (cmd >= batch_end) { DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); ret = -EINVAL;