| Message ID | 20161013105826.9710-8-mahesh1.kumar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu: > From: Mahesh Kumar <mahesh1.kumar@intel.com> > > This patch changes Watermak calculation to fixed point calculation. > Problem with current calculation is during plane_blocks_per_line > calculation we divide intermediate blocks with min_scanlines and > takes floor of the result because of integer operation. > hence we end-up assigning less blocks than required. Which leads to > flickers. > There are still variables that got auto-converted to 16.16 and need to be adjusted because later they are mixed with non-16.16 in non-safe ways. The fact that's it's hard to identify these things really worries me. > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c > index 0eaaadc..4263212 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3527,16 +3527,19 @@ static uint32_t skl_pipe_pixel_rate(const > struct intel_crtc_state *config) > * for the read latency) and cpp should always be <= 8, so that > * should allow pixel_rate up to ~2 GHz which seems sufficient since > max > * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. > + * Both Method1 & Method2 returns fixedpoint 16.16 output > */ > static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, > uint32_t latency) > { > - uint32_t wm_intermediate_val, ret; > + uint64_t wm_intermediate_val; > + uint32_t ret; > > if (latency == 0) > return UINT_MAX; > > - wm_intermediate_val = latency * pixel_rate * cpp / 512; > - ret = DIV_ROUND_UP(wm_intermediate_val, 1000); > + wm_intermediate_val = latency * pixel_rate * cpp; > + wm_intermediate_val <<= 16; > + ret = DIV_ROUND_UP_ULL(wm_intermediate_val, 1000 * 512); > > return ret; > } > @@ -3658,12 +3661,15 @@ static int skl_compute_plane_wm(const struct > drm_i915_private *dev_priv, > if (y_tiled) { > plane_blocks_per_line = > DIV_ROUND_UP(plane_bytes_per_line * > y_min_scanlines, 512); > - plane_blocks_per_line /= y_min_scanlines; > + plane_blocks_per_line = (plane_blocks_per_line << > 16) / > + y_mi > n_scanlines; > } else if (x_tiled) { > plane_blocks_per_line = > DIV_ROUND_UP(plane_bytes_per_line, 512); > + plane_blocks_per_line <<= 16; > } else { > plane_blocks_per_line = > DIV_ROUND_UP(plane_bytes_per_line, 512) > + 1; > + plane_blocks_per_line <<= 16; > } > > method1 = skl_wm_method1(plane_pixel_rate, cpp, latency); > @@ -3690,7 +3696,7 @@ static int skl_compute_plane_wm(const struct > drm_i915_private *dev_priv, > selected_result = method1; > } > > - res_blocks = selected_result + 1; > + res_blocks = DIV_ROUND_UP(selected_result, 1 << 16) + 1; > res_lines = DIV_ROUND_UP(selected_result, > plane_blocks_per_line); > > if (level >= 1 && level <= 7) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0eaaadc..4263212 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3527,16 +3527,19 @@ static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) * for the read latency) and cpp should always be <= 8, so that * should allow pixel_rate up to ~2 GHz which seems sufficient since max * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. + * Both Method1 & Method2 returns fixedpoint 16.16 output */ static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency) { - uint32_t wm_intermediate_val, ret; + uint64_t wm_intermediate_val; + uint32_t ret; if (latency == 0) return UINT_MAX; - wm_intermediate_val = latency * pixel_rate * cpp / 512; - ret = DIV_ROUND_UP(wm_intermediate_val, 1000); + wm_intermediate_val = latency * pixel_rate * cpp; + wm_intermediate_val <<= 16; + ret = DIV_ROUND_UP_ULL(wm_intermediate_val, 1000 * 512); return ret; } @@ -3658,12 +3661,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, if (y_tiled) { plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512); - plane_blocks_per_line /= y_min_scanlines; + plane_blocks_per_line = (plane_blocks_per_line << 16) / + y_min_scanlines; } else if (x_tiled) { plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); + plane_blocks_per_line <<= 16; } else { plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1; + plane_blocks_per_line <<= 16; } method1 = skl_wm_method1(plane_pixel_rate, cpp, latency); @@ -3690,7 +3696,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, selected_result = method1; } - res_blocks = selected_result + 1; + res_blocks = DIV_ROUND_UP(selected_result, 1 << 16) + 1; res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); if (level >= 1 && level <= 7) {