From patchwork Thu Oct 13 10:58:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Mahesh" X-Patchwork-Id: 9374755 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B74EB6075E for ; Thu, 13 Oct 2016 10:58:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A899B29FBC for ; Thu, 13 Oct 2016 10:58:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9CC4F29FBD; Thu, 13 Oct 2016 10:58:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3A75129FBE for ; Thu, 13 Oct 2016 10:58:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A4F286EA17; Thu, 13 Oct 2016 10:58:37 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0DAE16EA13 for ; Thu, 13 Oct 2016 10:58:28 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP; 13 Oct 2016 03:58:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,339,1473145200"; d="scan'208";a="19143018" Received: from kumarmah-desk.iind.intel.com ([10.223.26.44]) by fmsmga006.fm.intel.com with ESMTP; 13 Oct 2016 03:58:26 -0700 From: "Kumar, Mahesh" To: intel-gfx@lists.freedesktop.org Date: Thu, 13 Oct 2016 16:28:25 +0530 Message-Id: <20161013105826.9710-8-mahesh1.kumar@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161013105826.9710-1-mahesh1.kumar@intel.com> References: <20161013105826.9710-1-mahesh1.kumar@intel.com> Cc: paulo.r.zanoni@intel.com Subject: [Intel-gfx] [PATCH v4 7/8] drm/i915/skl+: change WM calc to fixed point 16.16 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Mahesh Kumar This patch changes Watermak calculation to fixed point calculation. Problem with current calculation is during plane_blocks_per_line calculation we divide intermediate blocks with min_scanlines and takes floor of the result because of integer operation. hence we end-up assigning less blocks than required. Which leads to flickers. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0eaaadc..4263212 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3527,16 +3527,19 @@ static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) * for the read latency) and cpp should always be <= 8, so that * should allow pixel_rate up to ~2 GHz which seems sufficient since max * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. + * Both Method1 & Method2 returns fixedpoint 16.16 output */ static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency) { - uint32_t wm_intermediate_val, ret; + uint64_t wm_intermediate_val; + uint32_t ret; if (latency == 0) return UINT_MAX; - wm_intermediate_val = latency * pixel_rate * cpp / 512; - ret = DIV_ROUND_UP(wm_intermediate_val, 1000); + wm_intermediate_val = latency * pixel_rate * cpp; + wm_intermediate_val <<= 16; + ret = DIV_ROUND_UP_ULL(wm_intermediate_val, 1000 * 512); return ret; } @@ -3658,12 +3661,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, if (y_tiled) { plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512); - plane_blocks_per_line /= y_min_scanlines; + plane_blocks_per_line = (plane_blocks_per_line << 16) / + y_min_scanlines; } else if (x_tiled) { plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); + plane_blocks_per_line <<= 16; } else { plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1; + plane_blocks_per_line <<= 16; } method1 = skl_wm_method1(plane_pixel_rate, cpp, latency); @@ -3690,7 +3696,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, selected_result = method1; } - res_blocks = selected_result + 1; + res_blocks = DIV_ROUND_UP(selected_result, 1 << 16) + 1; res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); if (level >= 1 && level <= 7) {