From patchwork Tue Oct 18 01:40:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenyu Wang X-Patchwork-Id: 9380999 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E311260487 for ; Tue, 18 Oct 2016 01:39:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D873228CBC for ; Tue, 18 Oct 2016 01:39:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CD481291A0; Tue, 18 Oct 2016 01:39:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A7B7428CBC for ; Tue, 18 Oct 2016 01:39:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BFDB56E35F; Tue, 18 Oct 2016 01:39:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id E995F6E35F for ; Tue, 18 Oct 2016 01:39:20 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP; 17 Oct 2016 18:39:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,359,1473145200"; d="scan'208";a="180829346" Received: from debian-skl.sh.intel.com ([10.239.159.29]) by fmsmga004.fm.intel.com with ESMTP; 17 Oct 2016 18:39:19 -0700 From: Zhenyu Wang To: daniel@ffwll.ch Date: Tue, 18 Oct 2016 09:40:07 +0800 Message-Id: <20161018014007.29369-1-zhenyuw@linux.intel.com> X-Mailer: git-send-email 2.9.3 Cc: intel-gfx@lists.freedesktop.org, zhiyuan.lv@intel.com Subject: [Intel-gfx] [PATCH] drm/i915/gvt: Fix build failure after intel_engine_cs change X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Change GVT-g code reference for intel_engine_cs from static array to allocated pointer after commit 3b3f1650b1ca ("drm/i915: Allocate intel_engine_cs structure only for the enabled engines"). Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/execlist.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/gvt/scheduler.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index 4a00ee7..c50a3d1 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -39,7 +39,7 @@ #define _EL_OFFSET_STATUS_PTR 0x3A0 #define execlist_ring_mmio(gvt, ring_id, offset) \ - (gvt->dev_priv->engine[ring_id].mmio_base + (offset)) + (gvt->dev_priv->engine[ring_id]->mmio_base + (offset)) #define valid_context(ctx) ((ctx)->valid) #define same_context(a, b) (((a)->context_id == (b)->context_id) && \ diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index d59a934..e8ec403 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -134,7 +134,7 @@ static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) reg &= ~GENMASK(11, 0); for (i = 0; i < I915_NUM_ENGINES; i++) { - if (gvt->dev_priv->engine[i].mmio_base == reg) + if (gvt->dev_priv->engine[i]->mmio_base == reg) return i; } return -1; diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 732672b..b15cdf5 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -68,7 +68,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload) workload->ctx_desc.lrca); context_page_num = intel_lr_context_size( - &gvt->dev_priv->engine[ring_id]); + gvt->dev_priv->engine[ring_id]); context_page_num = context_page_num >> PAGE_SHIFT; @@ -171,7 +171,7 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) shadow_ctx->desc_template = workload->ctx_desc.addressing_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; - workload->req = i915_gem_request_alloc(&dev_priv->engine[ring_id], + workload->req = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx); if (IS_ERR_OR_NULL(workload->req)) { gvt_err("fail to allocate gem request\n"); @@ -298,7 +298,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload) workload->ctx_desc.lrca); context_page_num = intel_lr_context_size( - &gvt->dev_priv->engine[ring_id]); + gvt->dev_priv->engine[ring_id]); context_page_num = context_page_num >> PAGE_SHIFT;