From patchwork Sat Oct 22 05:09:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenyu Wang X-Patchwork-Id: 9390363 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A4FDA600CB for ; Sat, 22 Oct 2016 05:14:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 964F228749 for ; Sat, 22 Oct 2016 05:14:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8A5A429DDA; Sat, 22 Oct 2016 05:14:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 31BCD28749 for ; Sat, 22 Oct 2016 05:14:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B44D06E1F4; Sat, 22 Oct 2016 05:14:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id EBA876E1EA; Sat, 22 Oct 2016 05:14:13 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP; 21 Oct 2016 22:14:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,528,1473145200"; d="asc'?scan'208";a="22434404" Received: from zhen-hp.sh.intel.com (HELO zhen-hp) ([10.239.13.134]) by orsmga005.jf.intel.com with ESMTP; 21 Oct 2016 22:14:04 -0700 Date: Sat, 22 Oct 2016 13:09:41 +0800 From: Zhenyu Wang To: Arnd Bergmann Message-ID: <20161022050941.q2wrkwqwob3izklg@zhen-hp.sh.intel.com> References: <20161021152620.3324407-1-arnd@arndb.de> <20161021152620.3324407-2-arnd@arndb.de> MIME-Version: 1.0 In-Reply-To: <20161021152620.3324407-2-arnd@arndb.de> User-Agent: NeoMutt/20160910 (1.7.0) Cc: dri-devel@lists.freedesktop.org, David Airlie , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Daniel Vetter , igvt-g-dev@lists.01.org Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/gvt: fix compilation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Zhenyu Wang Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On 2016.10.21 17:25:50 +0200, Arnd Bergmann wrote: > Two functions in the newly added gvt render code are obviously > broken, as they reference a variable without initialization and > don't reference another variable at all: > > drivers/gpu/drm/i915/gvt/render.c: In function ???intel_gvt_load_render_mmio???: > drivers/gpu/drm/i915/gvt/render.c:148:13: error: ???offset.reg??? may be used uninitialized in this function [-Werror=maybe-uninitialized] > drivers/gpu/drm/i915/gvt/render.c: In function ???intel_gvt_restore_render_mmio???: > drivers/gpu/drm/i915/gvt/render.c:185:13: error: ???offset.reg??? may be used uninitialized in this function [-Werror=maybe-uninitialized] > > This is probably not a correct fix, but it gets us a clean build > by removing the unused arrays and initializing the offset variable > to something that potentially might be correct. > > Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch") > Signed-off-by: Arnd Bergmann > --- I think the correct fix is like Thanks for pointing this out, it's a mistake during our code preparation for upstream. I'll queue this up. > drivers/gpu/drm/i915/gvt/render.c | 25 +++---------------------- > 1 file changed, 3 insertions(+), 22 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c > index feebb65ba641..79e112288065 100644 > --- a/drivers/gpu/drm/i915/gvt/render.c > +++ b/drivers/gpu/drm/i915/gvt/render.c > @@ -147,29 +147,20 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) > { > struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; > i915_reg_t offset, l3_offset; > - u32 regs[] = { > - [RCS] = 0xc800, > - [VCS] = 0xc900, > - [VCS2] = 0xca00, > - [BCS] = 0xcc00, > - [VECS] = 0xcb00, > - }; > int i; > > - if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) > - return; > - > if (!IS_SKYLAKE(dev_priv)) > return; > > for (i = 0; i < 64; i++) { > + offset.reg = i * 4; > gen9_render_mocs[ring_id][i] = I915_READ(offset); > I915_WRITE(offset, vgpu_vreg(vgpu, offset)); > POSTING_READ(offset); > - offset.reg += 4; > } > > if (ring_id == RCS) { > + offset.reg = 64 * 4; > l3_offset.reg = 0xb020; > for (i = 0; i < 32; i++) { > gen9_render_mocs_L3[i] = I915_READ(l3_offset); > @@ -184,26 +175,16 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) > { > struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; > i915_reg_t offset, l3_offset; > - u32 regs[] = { > - [RCS] = 0xc800, > - [VCS] = 0xc900, > - [VCS2] = 0xca00, > - [BCS] = 0xcc00, > - [VECS] = 0xcb00, > - }; > int i; > > - if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) > - return; > - > if (!IS_SKYLAKE(dev_priv)) > return; > > for (i = 0; i < 64; i++) { > + offset.reg = i * 4; > vgpu_vreg(vgpu, offset) = I915_READ(offset); > I915_WRITE(offset, gen9_render_mocs[ring_id][i]); > POSTING_READ(offset); > - offset.reg += 4; > } > > if (ring_id == RCS) { > -- > 2.9.0 > diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index feebb65..cc23c3f 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -162,6 +162,7 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) if (!IS_SKYLAKE(dev_priv)) return; + offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { gen9_render_mocs[ring_id][i] = I915_READ(offset); I915_WRITE(offset, vgpu_vreg(vgpu, offset)); @@ -199,6 +200,7 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) if (!IS_SKYLAKE(dev_priv)) return; + offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { vgpu_vreg(vgpu, offset) = I915_READ(offset); I915_WRITE(offset, gen9_render_mocs[ring_id][i]);