| Message ID | 20170210132959.16594-4-ander.conselvan.de.oliveira@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Feb 10, 2017 at 03:29:56PM +0200, Ander Conselvan de Oliveira wrote: > Implement WaDDIIOTimeout to avoid a timeout when enabling the DDI IO > power domains. > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 6 ++++++ > drivers/gpu/drm/i915/i915_reg.h | 5 +++++ > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ > 3 files changed, 21 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index ceb7699..bfccf9d 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2774,6 +2774,12 @@ intel_info(const struct drm_i915_private *dev_priv) > #define IS_KBL_REVID(dev_priv, since, until) \ > (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) > > +#define GLK_REVID_A0 0x0 > +#define GLK_REVID_A1 0x1 > + > +#define IS_GLK_REVID(dev_priv, since, until) \ > + (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) > + > /* > * The genX designation typically refers to the render engine, so render > * capability related checks should use IS_GEN, while display and other checks > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 141a5c1..ce6f096 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6495,6 +6495,11 @@ enum { > #define CHICKEN_PAR2_1 _MMIO(0x42090) > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) > > +#define CHICKEN_MISC_2 _MMIO(0x42084) > +#define GLK_CL0_PWR_DOWN (1 << 10) > +#define GLK_CL1_PWR_DOWN (1 << 11) > +#define GLK_CL2_PWR_DOWN (1 << 12) > + > #define _CHICKEN_PIPESL_1_A 0x420b0 > #define _CHICKEN_PIPESL_1_B 0x420b4 > #define HSW_FBCQ_DIS (1 << 22) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index c0b0f5a..6f2a95f 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -115,6 +115,16 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv) > */ > I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | > PWM1_GATING_DIS | PWM2_GATING_DIS); > + > + /* WaDDIIOTimeout:glk */ > + if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) { > + u32 val = I915_READ(CHICKEN_MISC_2); > + val &= ~(GLK_CL0_PWR_DOWN | > + GLK_CL1_PWR_DOWN | > + GLK_CL2_PWR_DOWN); > + I915_WRITE(CHICKEN_MISC_2, val); > + } > + > } > > static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) > -- > 2.9.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ceb7699..bfccf9d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2774,6 +2774,12 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_KBL_REVID(dev_priv, since, until) \ (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) +#define GLK_REVID_A0 0x0 +#define GLK_REVID_A1 0x1 + +#define IS_GLK_REVID(dev_priv, since, until) \ + (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) + /* * The genX designation typically refers to the render engine, so render * capability related checks should use IS_GEN, while display and other checks diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 141a5c1..ce6f096 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6495,6 +6495,11 @@ enum { #define CHICKEN_PAR2_1 _MMIO(0x42090) #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) +#define CHICKEN_MISC_2 _MMIO(0x42084) +#define GLK_CL0_PWR_DOWN (1 << 10) +#define GLK_CL1_PWR_DOWN (1 << 11) +#define GLK_CL2_PWR_DOWN (1 << 12) + #define _CHICKEN_PIPESL_1_A 0x420b0 #define _CHICKEN_PIPESL_1_B 0x420b4 #define HSW_FBCQ_DIS (1 << 22) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c0b0f5a..6f2a95f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -115,6 +115,16 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv) */ I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | PWM1_GATING_DIS | PWM2_GATING_DIS); + + /* WaDDIIOTimeout:glk */ + if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) { + u32 val = I915_READ(CHICKEN_MISC_2); + val &= ~(GLK_CL0_PWR_DOWN | + GLK_CL1_PWR_DOWN | + GLK_CL2_PWR_DOWN); + I915_WRITE(CHICKEN_MISC_2, val); + } + } static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
Implement WaDDIIOTimeout to avoid a timeout when enabling the DDI IO power domains. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 6 ++++++ drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ 3 files changed, 21 insertions(+)