From patchwork Fri Feb 10 13:29:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 9566767 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 80155601EA for ; Fri, 10 Feb 2017 13:30:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D13A28588 for ; Fri, 10 Feb 2017 13:30:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 622522858D; Fri, 10 Feb 2017 13:30:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E878E28588 for ; Fri, 10 Feb 2017 13:30:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5AA7D6ECEB; Fri, 10 Feb 2017 13:30:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id D388A6ECEB for ; Fri, 10 Feb 2017 13:30:21 +0000 (UTC) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Feb 2017 05:30:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,141,1484035200"; d="scan'208";a="63523791" Received: from linux.intel.com ([10.54.29.200]) by fmsmga005.fm.intel.com with ESMTP; 10 Feb 2017 05:30:21 -0800 Received: from localhost (aconselv-mobl3.fi.intel.com [10.237.66.52]) by linux.intel.com (Postfix) with ESMTP id EC8136A4080; Fri, 10 Feb 2017 05:29:19 -0800 (PST) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Fri, 10 Feb 2017 15:29:58 +0200 Message-Id: <20170210132959.16594-6-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170210132959.16594-1-ander.conselvan.de.oliveira@intel.com> References: <20170210132959.16594-1-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 5/6] drm/i915/glk: Don't attempt to sync DDI IO power well hw state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Geminilake's DDI IO power wells can only be enabled after a DPLL is running and must be disabled before disabling the DPLL. Attempting to change its state outside of this conditions will result in timeouts. That is the case when intel_power_domains_sync_hw() is called from intel_power_domains_init_hw(), where the attempt to disable the DDI IO for an enabled port will timeout, so don't attempt to sync the hw state for those power wells. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_runtime_pm.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index b729a39..4d2dc31 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2220,6 +2220,25 @@ static struct i915_power_well bxt_power_wells[] = { }, }; +static void noop_power_well_sync_hw(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ +} + +static const struct i915_power_well_ops glk_ddi_io_power_well_ops = { + /* + * DDI IO power wells in GLK can only be enabled after a DPLL is + * running and must be disabled before disabling the DPLL. Any + * attempt to change its state in different condidtions will lead + * to timeouts. + */ + .sync_hw = noop_power_well_sync_hw, + + .enable = skl_power_well_enable, + .disable = skl_power_well_disable, + .is_enabled = skl_power_well_enabled, +}; + static struct i915_power_well glk_power_wells[] = { { .name = "always-on", @@ -2288,19 +2307,19 @@ static struct i915_power_well glk_power_wells[] = { { .name = "DDI A power well", .domains = GLK_DISPLAY_DDI_A_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &glk_ddi_io_power_well_ops, .id = GLK_DISP_PW_DDI_A, }, { .name = "DDI B power well", .domains = GLK_DISPLAY_DDI_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &glk_ddi_io_power_well_ops, .id = SKL_DISP_PW_DDI_B, }, { .name = "DDI C power well", .domains = GLK_DISPLAY_DDI_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &glk_ddi_io_power_well_ops, .id = SKL_DISP_PW_DDI_C, }, };