From patchwork Wed Feb 15 14:48:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Mahesh" X-Patchwork-Id: 9574269 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E3850600F6 for ; Wed, 15 Feb 2017 14:57:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D4ABA28486 for ; Wed, 15 Feb 2017 14:57:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C935D284B4; Wed, 15 Feb 2017 14:57:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 49B22284A7 for ; Wed, 15 Feb 2017 14:57:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 347226E161; Wed, 15 Feb 2017 14:57:07 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2280F6E161 for ; Wed, 15 Feb 2017 14:57:05 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Feb 2017 06:57:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.35,166,1484035200"; d="scan'208"; a="1095068810" Received: from kumarmah-desk.iind.intel.com ([10.223.26.44]) by orsmga001.jf.intel.com with ESMTP; 15 Feb 2017 06:46:57 -0800 From: Mahesh Kumar To: intel-gfx@lists.freedesktop.org Date: Wed, 15 Feb 2017 20:18:39 +0530 Message-Id: <20170215144840.20461-3-mahesh1.kumar@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170215144840.20461-1-mahesh1.kumar@intel.com> References: <20170215144840.20461-1-mahesh1.kumar@intel.com> Cc: paulo.r.zanoni@intel.com, maarten.lankhorst@intel.com Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Decode system memory bandwidth X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support to decode system memory bandwidth which will be used for arbitrated display memory percentage calculation in GEN9 based system. Changes from v1: - Address comments from Paulo - implement decode function for SKL/KBL also Changes from v2: - Rewrite the code as per HW team inputs - Addresses review comments Changes from v3: - Fix compilation warning Changes from v4: - Address review comments from Paulo - Round-off the frequency & bandwidth results (Paulo) Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.c | 179 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 12 +++ drivers/gpu/drm/i915/i915_reg.h | 31 +++++++ 3 files changed, 222 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4c1cb067ca33..9203dad1db07 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -997,6 +997,179 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv) DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores)); } +static enum memdev_rank +skl_memdev_get_channel_rank(uint32_t val) +{ + uint8_t l_rank, s_rank; + uint8_t l_size, s_size; + + if (!val) + return I915_DRAM_RANK_INVALID; + + l_size = (val >> SKL_DRAM_SIZE_L_SHIFT) & SKL_DRAM_SIZE_MASK; + s_size = (val >> SKL_DRAM_SIZE_S_SHIFT) & SKL_DRAM_SIZE_MASK; + l_rank = (val >> SKL_DRAM_RANK_L_SHIFT) & SKL_DRAM_RANK_MASK; + s_rank = (val >> SKL_DRAM_RANK_S_SHIFT) & SKL_DRAM_RANK_MASK; + + if ((l_size == 0) && (s_size == 0)) + return I915_DRAM_RANK_INVALID; + + if (l_rank == SKL_DRAM_RANK_DUAL || s_rank == SKL_DRAM_RANK_DUAL) + return I915_DRAM_RANK_DUAL; + + if ((l_size && l_rank == SKL_DRAM_RANK_SINGLE) && + (s_size && s_rank == SKL_DRAM_RANK_SINGLE)) + return I915_DRAM_RANK_DUAL; + return I915_DRAM_RANK_SINGLE; +} + +static int +skl_get_memdev_info(struct drm_i915_private *dev_priv) +{ + struct memdev_info *memdev_info = &dev_priv->memdev_info; + uint32_t mem_freq_khz; + uint32_t val; + enum memdev_rank ch0_rank, ch1_rank; + + val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); + mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) * + SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000); + + val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); + ch0_rank = skl_memdev_get_channel_rank(val); + if (ch0_rank != I915_DRAM_RANK_INVALID) + memdev_info->num_channels++; + + val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); + ch1_rank = skl_memdev_get_channel_rank(val); + if (ch1_rank != I915_DRAM_RANK_INVALID) + memdev_info->num_channels++; + + if (memdev_info->num_channels == 0) { + DRM_ERROR("Number of memory channels is zero\n"); + return -EINVAL; + } + + memdev_info->bandwidth_kbps = memdev_info->num_channels * + mem_freq_khz * 8; + + if (memdev_info->bandwidth_kbps == 0) { + DRM_ERROR("Couldn't get system memory bandwidth\n"); + return -EINVAL; + } + + /* + * If any of the channel is single rank channel, worst case output + * will be same as if single rank memory, so consider single rank + * memory. + */ + if (ch0_rank == I915_DRAM_RANK_SINGLE + || ch1_rank == I915_DRAM_RANK_SINGLE) + memdev_info->rank = I915_DRAM_RANK_SINGLE; + else + memdev_info->rank = max(ch0_rank, ch1_rank); + + if (memdev_info->rank == I915_DRAM_RANK_INVALID) { + DRM_ERROR("couldn't get memory rank information\n"); + return -EINVAL; + } + + memdev_info->valid = true; + return 0; +} + +static int +bxt_get_memdev_info(struct drm_i915_private *dev_priv) +{ + struct memdev_info *memdev_info = &dev_priv->memdev_info; + uint32_t dram_channels; + uint32_t mem_freq_khz, val; + uint8_t num_active_channels; + int i; + + val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0); + mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) * + BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000); + + dram_channels = (val >> BXT_DRAM_CHANNEL_ACTIVE_SHIFT) & + BXT_DRAM_CHANNEL_ACTIVE_MASK; + num_active_channels = hweight32(dram_channels); + + /* Each active bit represents 4-byte channel */ + memdev_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4); + + if (memdev_info->bandwidth_kbps == 0) { + DRM_ERROR("Couldn't get system memory bandwidth\n"); + return -EINVAL; + } + + /* + * Now read each DUNIT8/9/10/11 to check the rank of each dimms. + */ + for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) { + val = I915_READ(BXT_D_CR_DRP0_DUNIT(i)); + if (val != 0xFFFFFFFF) { + uint8_t rank; + enum memdev_rank ch_rank; + + memdev_info->num_channels++; + rank = val & BXT_DRAM_RANK_MASK; + if (rank == BXT_DRAM_RANK_SINGLE) + ch_rank = I915_DRAM_RANK_SINGLE; + else if (rank == BXT_DRAM_RANK_DUAL) + ch_rank = I915_DRAM_RANK_DUAL; + else + ch_rank = I915_DRAM_RANK_INVALID; + + /* + * If any of the channel is single rank channel, + * worst case output will be same as if single rank + * memory, so consider single rank memory. + */ + if (memdev_info->rank == I915_DRAM_RANK_INVALID) + memdev_info->rank = ch_rank; + else if (ch_rank == I915_DRAM_RANK_SINGLE) + memdev_info->rank = I915_DRAM_RANK_SINGLE; + } + } + + if (memdev_info->rank == I915_DRAM_RANK_INVALID) { + DRM_ERROR("couldn't get memory rank information\n"); + return -EINVAL; + } + + memdev_info->valid = true; + return 0; +} + +static void +intel_get_memdev_info(struct drm_i915_private *dev_priv) +{ + struct memdev_info *memdev_info = &dev_priv->memdev_info; + int ret; + + memdev_info->valid = false; + memdev_info->rank = I915_DRAM_RANK_INVALID; + memdev_info->num_channels = 0; + + if (!IS_GEN9(dev_priv)) + return; + + if (IS_BROXTON(dev_priv)) + ret = bxt_get_memdev_info(dev_priv); + else + ret = skl_get_memdev_info(dev_priv); + if (ret) + return; + + DRM_DEBUG_DRIVER("DRAM bandwidth: %u KBps, total-channels: %u\n", + memdev_info->bandwidth_kbps, + memdev_info->num_channels); + DRM_DEBUG_DRIVER("DRAM rank: %s rank\n", + (memdev_info->rank == I915_DRAM_RANK_DUAL) ? + "dual" : "single"); +} + /** * i915_driver_init_hw - setup state requiring device access * @dev_priv: device private @@ -1103,6 +1276,12 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) if (ret) goto out_ggtt; + /* + * Fill the memdev structure to get the system raw bandwidth + * This will be used by WM algorithm, to implement GEN9 based WA + */ + intel_get_memdev_info(dev_priv); + return 0; out_ggtt: diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 918118a268b8..a88b2721dbe7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2384,6 +2384,18 @@ struct drm_i915_private { bool distrust_bios_wm; } wm; + struct memdev_info { + bool valid; + uint32_t bandwidth_kbps; + uint8_t num_channels; + enum memdev_rank { + I915_DRAM_RANK_INVALID = 0, + I915_DRAM_RANK_SINGLE, + I915_DRAM_RANK_DUAL + } rank; + } memdev_info; + + struct i915_runtime_pm pm; struct { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2ee26dc67053..8a3898c81a26 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8110,6 +8110,37 @@ enum { #define DC_STATE_DEBUG_MASK_CORES (1<<0) #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) +#define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114) +#define BXT_REQ_DATA_MASK 0x3F +#define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12 +#define BXT_DRAM_CHANNEL_ACTIVE_MASK 0xF +#define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333 + +#define BXT_D_CR_DRP0_DUNIT8 0x1000 +#define BXT_D_CR_DRP0_DUNIT9 0x1200 +#define BXT_D_CR_DRP0_DUNIT_START 8 +#define BXT_D_CR_DRP0_DUNIT_END 11 +#define _MMIO_MCHBAR_DUNIT(x, a, b) _MMIO(MCHBAR_MIRROR_BASE_SNB + (a) + (x - BXT_D_CR_DRP0_DUNIT_START)*((b)-(a))) +#define BXT_D_CR_DRP0_DUNIT(x) _MMIO_MCHBAR_DUNIT(x, BXT_D_CR_DRP0_DUNIT8, BXT_D_CR_DRP0_DUNIT9) +#define BXT_DRAM_RANK_MASK 0x3 +#define BXT_DRAM_RANK_SINGLE 0x1 +#define BXT_DRAM_RANK_DUAL 0x3 + +#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666 +#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04) +#define SKL_REQ_DATA_MASK (0xF << 0) + +#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) +#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) +#define SKL_DRAM_SIZE_MASK 0x3F +#define SKL_DRAM_SIZE_L_SHIFT 0 +#define SKL_DRAM_SIZE_S_SHIFT 16 +#define SKL_DRAM_RANK_MASK 0x1 +#define SKL_DRAM_RANK_L_SHIFT 10 +#define SKL_DRAM_RANK_S_SHIFT 26 +#define SKL_DRAM_RANK_SINGLE 0x0 +#define SKL_DRAM_RANK_DUAL 0x1 + /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, * since on HSW we can't write to it using I915_WRITE. */ #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)