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[86.3.57.50]) by smtp.gmail.com with ESMTPSA id s17sm2387305wrc.6.2017.02.22.08.37.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Feb 2017 08:37:08 -0800 (PST) From: Robert Bragg To: intel-gfx@lists.freedesktop.org Date: Wed, 22 Feb 2017 16:36:30 +0000 Message-Id: <20170222163634.7079-3-robert@sixbynine.org> X-Mailer: git-send-email 2.11.1 In-Reply-To: <20170222163634.7079-1-robert@sixbynine.org> References: <20170222163634.7079-1-robert@sixbynine.org> Subject: [Intel-gfx] [PATCH 2/6] drm/i915: expose _SUBSLICE_MASK GETPARM X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Assuming a uniform mask across all slices, this enables userspace to determine the specific sub slices enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW sub slice configuration. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_drv.c | 5 +++++ include/uapi/drm/i915_drm.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index d391768f301b..a497537b42d3 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -364,6 +364,11 @@ static int i915_getparam(struct drm_device *dev, void *data, if (!value) return -ENODEV; break; + case I915_PARAM_SUBSLICE_MASK: + value = INTEL_INFO(dev_priv)->sseu.subslice_mask; + if (!value) + return -ENODEV; + break; default: DRM_DEBUG("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index f47fb7f26f36..e0599e729e68 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -393,6 +393,7 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_MIN_EU_IN_POOL 39 #define I915_PARAM_MMAP_GTT_VERSION 40 #define I915_PARAM_SLICE_MASK 45 /* XXX: rebase before landing */ +#define I915_PARAM_SUBSLICE_MASK 46 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution * priorities and the driver will attempt to execute batches in priority order.