From patchwork Thu Feb 23 19:08:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Micha=C5=82_Winiarski?= X-Patchwork-Id: 9588849 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CE45660578 for ; Thu, 23 Feb 2017 19:09:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BD2322879A for ; Thu, 23 Feb 2017 19:09:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B2083287CE; Thu, 23 Feb 2017 19:09:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 614262879A for ; Thu, 23 Feb 2017 19:09:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E68366EB17; Thu, 23 Feb 2017 19:09:51 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id C50D36EB17 for ; Thu, 23 Feb 2017 19:09:50 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Feb 2017 11:09:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.35,198,1484035200"; d="scan'208"; a="1114781441" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by fmsmga001.fm.intel.com with ESMTP; 23 Feb 2017 11:09:49 -0800 Received: from mwiniars-main.igk.intel.com (172.28.171.152) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server id 14.3.248.2; Thu, 23 Feb 2017 19:09:47 +0000 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: Date: Thu, 23 Feb 2017 20:08:26 +0100 Message-ID: <20170223190833.2888-5-michal.winiarski@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170223190833.2888-1-michal.winiarski@intel.com> References: <20170223190833.2888-1-michal.winiarski@intel.com> MIME-Version: 1.0 X-Originating-IP: [172.28.171.152] Subject: [Intel-gfx] [RFC 04/11] drm/i915/preempt: Implement null preemption method X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP We're only requesting preemption for requests that have high enough priority (above threshold). Currently we're also ignoring requests that have dependencies on different engines. Signed-off-by: Michał Winiarski --- drivers/gpu/drm/i915/i915_guc_submission.c | 3 ++ drivers/gpu/drm/i915/intel_lrc.c | 81 +++++++++++++++++++++++++++++- 2 files changed, 83 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index feccd65..6d9431d 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -491,6 +491,9 @@ static int guc_ring_doorbell(struct i915_guc_client *client) static int i915_guc_preempt_noop(struct intel_engine_cs *engine) { + engine->preempt_requested = false; + intel_write_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX, 0); + return 0; } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index d4cfaa1..869b96e 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -674,16 +674,93 @@ pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) return engine; } +#define EXECLISTS_PREEMPT_THRESHOLD 512 + +static void __execlists_try_preempt(struct intel_engine_cs *engine, + int prio) +{ + struct drm_i915_gem_request *rq; + int highest_prio = INT_MIN; + int ret; + + spin_lock_irq(&engine->timeline->lock); + + /* Engine is idle */ + if (execlists_elsp_idle(engine)) + goto out_unlock; + + if (engine->preempt_requested) + goto out_unlock; + + list_for_each_entry_reverse(rq, &engine->timeline->requests, link) { + if (!i915_gem_request_completed(rq)) { + highest_prio = (rq->priotree.priority > highest_prio) ? + rq->priotree.priority : highest_prio; + } else + break; + } + + /* Bail out if our priority is lower than any of the inflight requests + * (also if there are none requests) */ + if (highest_prio == INT_MIN || prio <= highest_prio) + goto out_unlock; + + engine->preempt_requested = true; + + spin_unlock_irq(&engine->timeline->lock); + + ret = engine->preempt(engine); + if (ret) { + spin_lock_irq(&engine->timeline->lock); + engine->preempt_requested = false; + spin_unlock_irq(&engine->timeline->lock); + } + + return; + +out_unlock: + spin_unlock_irq(&engine->timeline->lock); +} + +static void execlists_try_preempt(struct intel_engine_cs *engine, + int prio, + unsigned long *engines_bumped) +{ + int num_engines_bumped = bitmap_weight(engines_bumped, + I915_NUM_ENGINES); + + /* Preemption is disabled */ + if (!engine->preempt) + return; + + /* We're not a high priority request */ + if (prio < EXECLISTS_PREEMPT_THRESHOLD) + return; + + /* We have dependencies on many engines */ + if (num_engines_bumped > 1) + return; + + /* We have dependency on a single engine - but it's not our engine */ + if (num_engines_bumped == 1 && !test_bit(engine->id, engines_bumped)) + return; + + __execlists_try_preempt(engine, prio); +} + static void execlists_schedule(struct drm_i915_gem_request *request, int prio) { struct intel_engine_cs *engine = NULL; struct i915_dependency *dep, *p; struct i915_dependency stack; LIST_HEAD(dfs); + DECLARE_BITMAP(engine_bumped, I915_NUM_ENGINES); if (prio <= READ_ONCE(request->priotree.priority)) return; + bitmap_zero(engine_bumped, I915_NUM_ENGINES); + /* Need BKL in order to use the temporary link inside i915_dependency */ lockdep_assert_held(&request->i915->drm.struct_mutex); @@ -719,6 +796,7 @@ static void execlists_schedule(struct drm_i915_gem_request *request, int prio) continue; engine = pt_lock_engine(pt, engine); + __set_bit(engine->id, engine_bumped); /* If it is not already in the rbtree, we can update the * priority inplace and skip over it (and its dependencies) @@ -737,6 +815,7 @@ static void execlists_schedule(struct drm_i915_gem_request *request, int prio) INIT_LIST_HEAD(&dep->dfs_link); engine = pt_lock_engine(pt, engine); + __set_bit(engine->id, engine_bumped); if (prio <= pt->priority) continue; @@ -752,7 +831,7 @@ static void execlists_schedule(struct drm_i915_gem_request *request, int prio) if (engine) spin_unlock_irq(&engine->timeline->lock); - /* XXX Do we need to preempt to make room for us and our deps? */ + execlists_try_preempt(engine, prio, engine_bumped); } static int execlists_context_pin(struct intel_engine_cs *engine,